Suresh Kancharana — Software Engineer

Strong basics in ASIC complete process, starting from RTL design to packaging techniques. Mostly focused on Physical Design, static timing analysis(STA), constraints generation, floorplan creation, synthesis, DFT insertion, UPF creation, equivalency checks and power checks. -> Responsible for delivering AI/ML CPU (DPU/TPU) core to support ARM v9 instruction set. -> Responsible for delivering DDR5/DDR4 multi-channel DDR memory controller subsystem from SYN to GDS. -> Responsible for delivering pcie interface subsystem for on-die and off-die communication. -> Developed a Scalable PnR implementation for high frequency CMN-Bus to achieve best PPA and to meet server chip frequency targets with a novel strategy, which is later adopted for bus implementation across this server SoC. -> Responsible for developing the SoC level upf strategy to resolve frontend and backend tool-supported low power updates. -> Responsible for DDR subsystem level Floorplan partitioning and PNR implementation. -> Responsible for chip level static timing analysis and timing closure. -> Responsible for Block level Place & Route activities on high performance challenging design. -> Timing closure for mobile SoCs using Synopsys Prime-Time in cutting-edge technologies (28nm, 20nm, 16nm, 10nm, 7nm, 5nm, 4nm and 3nm). -> Responsible for synthesis and floorplan guidance for timing critical (& memory-dense) modules using Synopsys Design-Compiler Graphical. -> Responsible for chip level UPF creation. -> Hands on industrial experience in floorplan partitioning, PNR, STA, synthesis, constraints development and UPF creations. Good knowledge on Macroarchitecture & Microarchitecture of complex designs. Learnt challenging design techniques while design & implementing high frame rate architecture for Face-detection on FPGA. skills: Programming: C, tcl, perl, matlab HDL: Verilog, Bluespec System Verilog. EDA Tools: Innvous, Genus, Tempus, Prime-Time, Design-Compiler, ICCompiler, Tweaker, Time-Vision, Conformal-LEC, Conformal-low power check(CLP), MVRC, Formality, Mentor-Graphics (Layout) tools. About me: Focused, interested to learn and teach new things.

Stackforce AI infers this person is a highly skilled ASIC design engineer with expertise in physical design and timing analysis.

Location: Bengaluru, Karnataka, India

Experience: 14 yrs 6 mos