Poornima Shanbhogue

Software Engineer

San Jose, California, United States8 yrs 11 mos experience

Key Highlights

Expert in Static Timing Analysis and Physical Design.
Hands-on experience with ASIC and SoC design.
Strong background in VLSI and digital systems.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC and Physical Design.

Contact

Skills

Core Skills

Static Timing AnalysisPhysical DesignTiming Analysis

Other Skills

PerlLinuxApplication-Specific Integrated Circuits (ASIC)Shell ScriptingVerilogSynopsys PrimetimeLogic DesignFloorplanningCTSCMOSSystem on a Chip (SoC)Low-power DesignLogic SynthesisTCLPower Plan

Experience

8 yrs 11 mos

Total Experience

Average Tenure

Current Experience

Samsung semiconductor

2 roles

Senior Engineer

Jan 2023 – Present · 3 yrs 5 mos · San Jose, California, United States

Static Timing AnalysisPerlLinuxApplication-Specific Integrated Circuits (ASIC)Shell ScriptingVerilog+10

STA Intern

Jun 2022 – Dec 2022 · 6 mos · San Jose, California, United States

Mediatek

3 roles

Physical Design and Timing Intern

Jan 2022 – May 2022 · 4 mos · United States

Senior Engineer

Promoted

Jun 2020 – Jan 2021 · 7 mos

Engineer

Nov 2017 – May 2020 · 2 yrs 6 mos

STA and Synthesis Engineer

San jose state university

Masters in Electrical Engineering

Jan 2021 – Dec 2022 · 1 yr 11 mos · San Jose, CA, United States

Master’s in Electrical Engineering Focusing on the Design of Digital Systems/ASIC.

Rv-vlsi vlsi and embedded systems design center

Graduate Engineering Trainee - Physical Design

Mar 2017 – Sep 2017 · 6 mos · Bangalore

Performed timing analysis on a design, analyzed and fixed setup and hold violations for different path groups.
Worked on the block level implementation of subsystem including freezing the floorplan, power plan, placement of standard cells and synthesized the clock tree.