S

Suvi Jain

Frontend Engineer

Bengaluru, Karnataka, India9 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in RTL design and physical design methodologies.
  • Proficient in automation tasks for design and analysis.
  • Strong background in timing analysis and verification.
Stackforce AI infers this person is a Semiconductor Engineering professional with expertise in RTL and Physical Design.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignPhysical DesignTiming Analysis

Other Skills

synthesisSTAFVautomationCadence SoftwareTCLFloorplanningSystemVerilogLayout Versus Schematic (LVS)PerlDesign Rule Checking (DRC)Place & RoutePhysical VerificationShell ScriptingTiming Closure

About

Currently, I am working as a front end engineer responsible for RTL design, synthesis, STA and FV of various macros for Custom and semi-custom implementation team. I have also worked as a Physical Design and STA engineer designing memory Intellectual properties (IPs) like L2. I am also responsible for various automation tasks required for the design and analysis of IPs. I have worked in field of RTL generation and integration at Intel.

Experience

9 yrs 3 mos
Total Experience
3 yrs
Average Tenure
8 yrs
Current Experience

Qualcomm

4 roles

Staff Engineer

Promoted

Dec 2025 – Present · 5 mos

  • I am currently working as a Front-end engineer responsible for RTL design, synthesis, STA, FV, etc. for various IPs. I have also worked as a Physical Design engineer designing memory based IPs like L2 and also performed automation for such custom designs. I am also responsible for various automation tasks.
RTL designsynthesisSTAFVautomationRTL Design+1

Senior Lead Engineer

Dec 2022 – Dec 2025 · 3 yrs

Cadence SoftwareTCLFloorplanningPhysical DesignSystemVerilogLayout Versus Schematic (LVS)+14

Senior Engineer

Dec 2020 – Dec 2022 · 2 yrs

Cadence SoftwareFloorplanningPhysical DesignLayout Versus Schematic (LVS)Design Rule Checking (DRC)Place & Route+6

Engineer

Jun 2018 – Dec 2020 · 2 yrs 6 mos

Cadence SoftwareFloorplanningPhysical DesignLayout Versus Schematic (LVS)Design Rule Checking (DRC)Place & Route+6

Intel corporation

SoC Design Engineer

Jul 2017 – May 2018 · 10 mos

Shell Scripting

Qualcomm

Interim Engineering Intern

Jan 2017 – Jun 2017 · 5 mos · Bengaluru, Karnataka, India

  • Worked as part of Automation team of Standard Cell team.
  • Delivered scripts using PERL and SKILL supporting various layout teams.
PERLSKILL

Delhi metro rail corporation ltd

Summer Intern

Jun 2014 – Jul 2014 · 1 mo · Shashtri Park Depot, Delhi

  • PA/PIS (public announcement and public information system)

Power grid corporation of india limited

Summer Intern

Jun 2013 – Jul 2013 · 1 mo · Katwaria Sarai, Delhi

  • SCADA Management

Education

Birla Institute of Technology and Science, Pilani

Master of Engineering (M.Eng.) — Microelectronics

Jan 2015 – Jan 2017

Indira Gandhi Delhi Technical University for Women

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2011 – Jan 2015

Stackforce found 100+ more professionals with Rtl Design & Physical Design

Explore similar profiles based on matching skills and experience

PJ

Prasoon Jain

IC design

at Intel Corporation

India24 yrs 9 mos exp
KD

Kapil Raj Dangeti

Senior Design Engineer

at AMD

India19 yrs 3 mos exp
ASICVLSI
Manoz T

Manoz T

SoC Design Engineer

at Intel Corporation

Bengaluru, India20 yrs 4 mos exp
Pradeep Mishra

Pradeep Mishra

Engineering Director

at Intel Corporation

Bengaluru, India30 yrs 1 mo exp
VLSIMixed Signal
vikas agrawal

vikas agrawal

Asic Engineer Emulation

at Meta

Bengaluru, India19 yrs 6 mos exp
ASICFunctional Verification
Dimple Lalwani

Dimple Lalwani

ASIC Design Engineer

at Meta

Bengaluru, India18 yrs 7 mos exp
SoCASIC
Kiran Patel

Kiran Patel

Technical Program Manager

at Intel Corporation

Bengaluru, India24 yrs 11 mos exp
Project ManagementVLSI
VJ

Venugopal Jennarapu

VP of Engineering

at SiliConch Systems

Bengaluru, India21 yrs 8 mos exp
VLSIFunctional Verification