Talari Prem Sai

Product Engineer

Pulivendla, Andhra Pradesh, India5 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in VLSI design and static timing analysis.
  • Proficient in physical design tools and methodologies.
  • Strong background in clock tree synthesis and floorplanning.
Stackforce AI infers this person is a VLSI design engineer with expertise in physical design and timing analysis.

Contact

Skills

Core Skills

Very-large-scale Integration (vlsi)Static Timing Analysis

Other Skills

physical design flowSTA conceptssynopsys prime timesynopsys icc2Intel Quartus primeClock Tree SynthesisFloorplanningLogic DesignLinuxPerlTCLMOSFETTimingPlace & Routepower planning

About

skills: physical design flow STA concepts Tools: synopsys prime time synopsys icc2 Intel Quartus prime

Experience

5 yrs 10 mos
Total Experience
1 yr 11 mos
Average Tenure
2 yrs 1 mo
Current Experience

Amd

Design engineer II

Apr 2024Present · 2 yrs 1 mo · Bengaluru, Karnataka, India

physical design flowSTA conceptssynopsys prime timesynopsys icc2Intel Quartus primeVery-Large-Scale Integration (VLSI)+1

Smartsoc solutions pvt ltd

Engineer II

Jan 2021Apr 2024 · 3 yrs 3 mos · Bengaluru, Karnataka, India

Clock Tree SynthesisFloorplanningVery-Large-Scale Integration (VLSI)

Rv-vlsi vlsi and embedded systems design center

Trainee

Aug 2019Feb 2020 · 6 mos · bangalore

Education

Rajeev Gandhi Memorial College Of Engineering & Technology

Bachelor of Technology - BTech

Jan 2015Jan 2019

sri chaitanya junior college ,vijayawada

MPC — MPC

Jan 2013Jan 2015

Narayana High school pulivendula

Jan 2013Present

Stackforce found 100+ more professionals with Very-large-scale Integration (vlsi) & Static Timing Analysis

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