VAIBHAV PAWALE

Software Engineer

Pune, Maharashtra, India2 yrs 1 mo experience
Highly Stable

Key Highlights

  • Expertise in advanced semiconductor nodes.
  • Strong foundation in VLSI and signal processing.
  • Hands-on experience in physical design engineering.
Stackforce AI infers this person is a VLSI Design Engineer with a focus on semiconductor technology.

Contact

LinkedIn

Skills

Core Skills

Physical Design

Other Skills

Static Timing AnalysisDigital ElectronicsCircuit AnalysisVery-Large-Scale Integration (VLSI)Physical VerificationUnixTCL

About

I’m a 2023 B.Tech Electronics & Telecommunications graduate from VIT Pune, working as a Physical Design Engineer in memory interface group at Cadence Design Systems. My expertise spans advanced nodes across major foundries: • Samsung: 4nm, 5nm • TSMC: 3nm • Intel: 1.8nm, 22nm Passionate about VLSI, digital/analog design, and signal processing, I aim to contribute to cutting-edge semiconductor innovations that push the limits of technology.

Experience

2 yrs 1 mo
Total Experience
2 yrs 1 mo
Average Tenure
2 yrs 1 mo
Current Experience

Cadence design systems

2 roles

Design Engineer I

May 2024 – Present · 2 yrs 1 mo · Pune · On-site

Physical DesignStatic Timing Analysis

Physical Design Intern

Jan 2023 – Jul 2023 · 6 mos · Pune, Maharashtra, India · On-site

Education

BITS Pilani Work Integrated Learning Programmes

Master of Technology - MTech — VLSI Design & Microelectronics

Jan 2026 – Jan 2028

Vishwakarma Institute Of Technology

Bachelor's degree — Electronics and Communications Engineering

Jan 2019 – Jan 2023

Jawahar Navodaya Vidyalaya - JNV

12th — CBSE

Jan 2018 – Jan 2019

Jawahar Navodaya Vidyalaya - JNV

10th — CBSE

Jan 2016 – Jan 2017

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VAIBHAV PAWALE - Software Engineer | Stackforce