Velmurugan A.

CEO

Bengaluru, Karnataka, India14 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 12 years of FPGA development experience.
  • Active contributor to multiple standard communities.
  • Expertise in high-speed design and wireless charging systems.
Stackforce AI infers this person is a specialist in Electronics with a focus on FPGA development and wireless charging technologies.

Contact

Skills

Core Skills

FpgaRtl DesignUsb PdWireless ChargingHdmiDsp

Other Skills

USB3.0PCIeADCI2CSPIDMADDRASKFSKWPCDPPWMFIRCORDICFIR Filter

About

Experienced FPGA Development Manager with over 12 years of expertise in FPGA-based product development, from requirement analysis to final product support. Skilled in architecture/micro-architecture design, Verilog/VHDL implementation, and testing on hardware. Active contributor to various standard communities including USB-IF, WPC, VESA, HDMI, and PCI-SIG. SKILS Languages: Verilog, VHDL, C Tools: Vivado/ISE, Quartus Prime Pro, Lattice Diamond/iCEcube, ModelSim/ActiveHDL/iSim, Xilinx System Generator/MATLAB. Protocols: USB PD, USB 3.2, USB 2, DP1.4a, Qi2/WPC/BPP/EPP/MPP25, PCIe, USB4-PHY, DDR, SPI, I2C, UART Design: High-Speed Design, SERDES, ARM, AXI, Avalon, DDS, FIR, ASK, FSK, EYE PLOT, BERT DSP: RADAR, EV and wireless Charging System (DDC, Freq Synth, IQ Mod, FIR/CIC/FFT) FPGA Platforms: Stratix 10, Arria 10, MPSoC, ZYNQ, KINTEX 7, VERTIX 4, SPARTEN 3E, Cool Runner II, Lattice XP2, LCMXO2, iCE5LP1K, ICE40LP8K

Experience

14 yrs 4 mos
Total Experience
4 yrs 9 mos
Average Tenure
8 yrs 7 mos
Current Experience

Granite river labs inc.

2 roles

FPGA/RTL Development Manager

Promoted

Apr 2019Present · 7 yrs 2 mos

  • Leads FPGA RTL architecture and implementation for USB Power Delivery/Type-C Tester (GRL-USB-PD-C2), incorporating PPS, DP AUX, Quick Charge, ADC/I2C/SPI/DAC interfaces, ARM SoC interconnect, DMA/DDR memory management, and FW/SW integration.
  • Developed GRL WPC Qi Wireless Charging Base Station Tester (GRL-WP-BST-C3) supporting BPP/EPP profiles up to Qi v1.3, with ASK/FSK modulation-demodulation and multi-packet handling capabilities.
  • Architected RTL Modules for EPR variant of USB-PD tester (GRL-USB-PD-C2-EPR) for extended power range applications.
  • Designed Sideband Emulator Analyzer for HDMI/DP over USB-C, handling SBU interface, DDC/I2C, and DP-AUX protocols.
  • Architected RTL Modules for Qi2 Wireless Charging Transmitter/Receiver Test Solution (GRL-C3-MP-TPR/TPT), featuring MPP, ASK demodulation, DDS, IQ demodulation, FIR/CORDIC filters, PWM phase shift/duty/frequency/dither controls, ARM-AXI interface, and DDR-DMA.
  • Knowledge on high-speed protocol test solutions for DP 1.4a, USB 3.2, and USB4, including AUX/SERDES/SBU, LFPS/OOB signaling, BERT, encoder/scrambler, RS-FEC, link training, and PCIe/AXI/Avalon interfaces
USB3.0PCIeFPGARTL Design

Technical Lead (FPGA/RTL)

Oct 2017Mar 2019 · 1 yr 5 mos

FIR FilterVerilogFPGARTL Design

Intsemi technologies private limited

Senior FPGA Design Engineer

Feb 2016Sep 2017 · 1 yr 7 mos · Bangalore · On-site

  • Implemented Foreign Object Detector (VHDL, Lattice XP2), 100Hz Low Pass Filter (distributed arithmetic, Blackman Harris window), Digital Down Converter for Magnetic Vectoring Receiver (NCO, multiplier, ADC interface).
FIR FilterDSPFPGA

Bharat electronics

Project Engineer (Contract)

Dec 2011Feb 2016 · 4 yrs 2 mos · Bengaluru Area, India

FIR FilterDSP

Education

Anna University Coimbatore

Bachelor of Engineering (B.E.) — Electronics and Communications Engineering

Jan 2008Jan 2011

Thanapandian Polytechnic College

Diploma — Electronics and Communications Engineering

Jan 2005Jan 2008

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