Venkata Durga Prabhas Allacheruvu — Software Engineer

ASIC Design Verification Engineer with hands-on experience in SoC and IP-level verification using SystemVerilog and UVM, currently working in SpanIdea for Client Broadcom Previously at Synopsys, I worked as a Verification & Validation Engineer on next-generation VCS simulation technologies, validating large SoC-level UVM environments used by leading semiconductor companies such as NVIDIA and MediaTek. This role gave me deep exposure to real-world customer designs, large regressions, coverage closure, and complex debug scenarios. I bring a strong verification-first mindset, combining: -> Solid UVM architecture understanding -> Deep debug skills using VCS & Verdi -> Experience with performance, scalability, and regression stability -> Automation skills using Python (and Perl) to improve DV efficiency 🔧 Core Skills: SystemVerilog | UVM | ASIC / SoC Verification | VCS | Verdi | AXI Coverage-Driven Verification | Assertions (SVA) | Python Automation 🎯 Interests: IP / SoC Design Verification roles in high-performance compute, networking, AI, and data-center silicon. 📩 Always open to meaningful technical discussions, collaboration, and referrals in the DV space.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and SoC validation.

Location: Guntur, Andhra Pradesh, India

Experience: 1 yr 11 mos