Venkatesh V.

Software Engineer

Bengaluru, Karnataka, India5 yrs 6 mos experience

Key Highlights

  • Expert in Physical Design and Timing Closure.
  • Experience with leading semiconductor companies.
  • Proficient in advanced design tools like Fusion Compiler.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignTiming Closure

Other Skills

Fusion CompilerTiming debugClock Tree SynthesisFloorplanningPhysical VerificationSynopsys PrimetimeFloorplan to SignoffFloorplanPNRECOTiming AnalysisTCLDigital ElectronicsunixMicrosoft Office

Experience

5 yrs 6 mos
Total Experience
1 yr 3 mos
Average Tenure
11 mos
Current Experience

Synopsys inc

Application Engineer, Staff

Jul 2025 – Present · 11 mos · Bengaluru, Karnataka, India

Fusion CompilerTiming debugPhysical DesignClock Tree SynthesisTiming Closure

Mediatek

Physical Design Engineer : Contractor

Feb 2024 – Jul 2025 · 1 yr 5 mos · Bengaluru, Karnataka, India · On-site

FloorplanningTiming ClosureClock Tree SynthesisPhysical VerificationSynopsys PrimetimeFloorplan to Signoff+1

Arm

Physical Design Engineer : Consultant

Jul 2023 – Dec 2023 · 5 mos · Bengaluru, Karnataka, India

Adept chip services pvt ltd

Physical Design Engineer (AMD ODC)

Feb 2022 – Dec 2023 · 1 yr 10 mos · Bengaluru, Karnataka, India

  • Client : AMD
  • Working on latest technology nodes.
  • Handling block level Floorplan to Signoff.
FloorplanPNRECOTiming AnalysisPhysical Design

Intel corporation

Physical Design Engineer

Sep 2020 – Jan 2022 · 1 yr 4 mos · Bengaluru, Karnataka, India

ECOTiming AnalysisPhysical Design

Indian institute of science (iisc)

Intern

Jul 2018 – Sep 2018 · 2 mos

Education

Visvesvaraya Technological University

Electrical and Electronics Engineering

Jan 2015 – Jan 2019

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