Jul 2012 – Jun 2013 · 11 mos · Hyderabad Area, India

• I have worked on two projects, which are SOCS(system on a chip).
• Also worked on physical design of two blocks which are 1 million in instance count each.
• Responsibilities:
• PnR flow with congestion less floorplan modeling, performing IR Drop & EM Analysis.
• Clock Tree synthesis was done meeting the required latency as per the specification.
• STA timing closure was done for different corners
• Budgeting the sdc
• Technology/Tools: 28nm Technology, SOC Encounter, ICC, Sierra Pinnacle.

Jun 2010 – Jul 2012 · 2 yrs 1 mo · Bengaluru Area, India

• 1. During this phase of my career, i worked on the design of high speed IO circuits and their integrations, for the family of processors like POWER processors and system Z processor.
• 2. My job responsibilities include, Synthesis, PnR for various blocks of IO Units, timing closure i.e. STA and Physical verification
• 3. And within an year I started leading the design of IPs and their integration for IO units like IOD, IOE, IOG for the chips like P7+, P8(venice), salerno, ZG, ZG+.
• 4. Technology/Tools : 22nm, 32nm Technology, Einsteimer, PDSRTL, RAPIDS, FINALE, QRC, CALIBRE.