Yudhishthira Kundu

CEO

Bengaluru, Karnataka, India25 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Proven track record in ASIC and FPGA product development.
  • Expertise in telecom network architecture and design.
  • Strong leadership in managing multi-location teams.
Stackforce AI infers this person is a Telecom ASIC and FPGA expert with extensive leadership experience.

Contact

Skills

Core Skills

FpgaTelecomAsicRtl Design

Other Skills

Multi-Gigabits designEmulation frameworkLoad driven clockingL2 CacheIPSecVoIPOLT GPON MACProduct verificationTest leadValidationOC-N FramingEoS chipTFI5 IPVirtual ConnectionECO back-annotation

About

Experienced in Defining, Architecting, Developing, Directing and Delivering ASIC, FPGA products. A self-motivated, results-driven individual. Lead by focusing relentlessly on goals, and directing and building teams that embrace challenging goals and deliver to commitments. Expertise spans across conceptualization to commercialization of core networking, wireless/mobile, clients, servers and xRAN products. A proactive leader with a proven track record of developing multiple successful multi-million gate ASICs for Telecom network (Core, xRAN), Mobile Station Modems, Client, Server, Edge and multi-location team management. Possess good problem solving and analytical skills and have talent for innovation, execution and negotiation. Adopt a motivational management style to create a work environment to enhance productivity with a record of building and retaining highly motivated team. Have outstanding process/methodology improvement and project management skills. A balance of technical competence, project execution skill and leadership.

Experience

25 yrs 2 mos
Total Experience
8 yrs 4 mos
Average Tenure
9 yrs 7 mos
Current Experience

Intel corporation

Senior Director

Nov 2016Present · 9 yrs 7 mos · Bengaluru, Karnataka, India

Qualcomm

Principal Engineer

Feb 2012Nov 2016 · 4 yrs 9 mos · Bangalore

Transwitch

4 roles

Project Manager (Principal Member Technical Staff)

Sep 2009Feb 2012 · 2 yrs 5 mos

  • Multi-Gigabits FPGA design implementations
  • Emulation framework for a router chip
  • Load driven clocking, L2 Cache, SDIO, IPSec related work for High Capacity VoIP chip
FPGAMulti-Gigabits designEmulation frameworkLoad driven clockingL2 CacheIPSec+2

Senior Member Technical Staff

Jan 2006Aug 2009 · 3 yrs 7 mos

  • Architecture & Design OLT GPON MAC
  • Product verification and Test lead for ONT SoC
  • Validation of ONT SoC
OLT GPON MACProduct verificationTest leadValidationTelecomASIC

Member Technical Staff

Promoted

Jan 2003Dec 2005 · 2 yrs 11 mos

  • Architecture, Design and Development OC-N Framing Frontend for EoS chip
  • Validation of EoS chip
  • Architecture, Design and Development of TFI5 IP
  • Architecture, Design and Development of Aligner and Pointer Processing IP
  • Architecture, Design and Development of Virtual Concatnetion/Link Capacicty adjustment scheme
OC-N FramingEoS chipTFI5 IPVirtual ConnectionTelecomASIC

Associate Member Technical Staff

Jan 2001Dec 2002 · 1 yr 11 mos

  • Architecture, Design and Development of OC-N Framing FrontEnd
  • RTL Design for SPCOMBUS
  • ECO back-annotation
RTL DesignECO back-annotationASIC

Education

Indian Institute of Management, Lucknow

GMPE

Jan 2011Jan 2012

Army Institute of Technology

B.E. — Electronics and Telecommunication

Jan 1996Jan 2000

DAV College, Chandigarh

Senior Secondary

Jan 1994Jan 1996

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