Christian Leber

CTO

Chicago, Illinois, United States21 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Led R&D team for custom hardware in trading applications.
Expert in FPGA and ASIC design for high-performance systems.
Developed low-latency trading solutions for financial markets.

Stackforce AI infers this person is a Fintech expert specializing in high-performance computing and low-latency trading systems.

Contact

dezgbolt@hotmail.com LinkedIn

Skills

Core Skills

Engineering LeadershipComputer ArchitectureFpgaSimulation

Other Skills

ASICAlgorithmic TradingAlgorithmsApplication-Specific Integrated Circuits (ASIC)ArchitectureBring-upBusinessCC++Computer ScienceCryptographyDesignDevice DriversDigital DesignsDistributed Systems

About

Currently I am leading a team of R&D engineers in the pursuit to built custom hardware for trading applications. I am experienced in the design, development and deployment of optimized computer architectures that make efficient use of custom hardware structures and optimized software. Before joining IMC I have worked on components for a HPC network (Extoll) at the computer architecture group of the University of Heidelberg. Specialties: building strong teams, hybrid hardware/software systems, simulation, FPGA, EDA, ASIC design, bring up, testing, modeling, design analysis, computer architecture, distributed algorithms, interconnection networks, HPC, communications, network topologies, verification, optimization, parallel computation, design automation, cryptographic protocols, low latency, HFT, trading execution system

Experience

Imc - financial markets

3 roles

Hardware R&D Lead

Jan 2018 – Present · 8 yrs 2 mos

Engineering LeadershipEngineering ManagementTeam LeadershipArchitectureMicroarchitectureDigital Designs+42

Hardware R&D Lead

Promoted

Jun 2017 – Dec 2017 · 6 mos

Hardware Engineer / Performance Engineer

Dec 2012 – May 2017 · 4 yrs 5 mos

University of heidelberg

2 roles

Research Fellow

Aug 2012 – Nov 2012 · 3 mos

Research Associate

Jan 2008 – Aug 2012 · 4 yrs 7 mos

Computer Architecture Group of Prof. Dr. Ulrich Bruening
Development of a PCI express High Performance Flash device based on an FPGA with 24 independent controllers, each controlling four NAND chips
Supervision of multiple diploma thesis, student talks and projects. Organized exercises for lectures.
Worked on a chipset implementation for AMD Opteron processors within an FPGA and modified coreboot (BIOS) for this purpose.
Specification, design and implementation of components for the EXTOLL HPC network. This components are a fast address translation unit and a novel unit that pushes status information from hardware to the software in an efficient way.
Design, implementation and bring-up of a complex FPGA trading accelerator
design. UDP, FAST were implemented in hardware on the stream side. The
ordering side uses a hybrid hardware/software TCP/IP implementation to
lower the latency.
A simulation environment was developed to test the trading accelerator de-
sign with trading software in a hardware simulator.