Vishal Bhatt

Software Engineer

Bengaluru, Karnataka, India18 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

17 years of experience in Micro architecture & RTL design.
Expertise in Verilog, RTL Synthesis, and Static Timing Analysis.
Multiple ASIC Tape-out experience across various domains.

Stackforce AI infers this person is a highly skilled ASIC design engineer with extensive experience in micro-architecture and RTL design.

Contact

Skills

Other Skills

Functional VerificationDebuggingLogic SynthesisMicroprocessorsICFPGAVLSIProcessorsDFTDDR2Computer ArchitectureUSBDDRAMBA AHBModelSim

About

Have more than 17 years of experience in Micro architecture & RTL design of IPs and Subsystems in various domains like IO-MMU, High Speed Serial Interfaces (USB/PCIe), Computer networking (L2/L3 switches), Cache coherence etc. worked on high performance deeply pipelined designs for ASICs Expertise in Verilog, RTL Synthesis,CDC Analysis, STA and LEC. Good working knowledge in DFT/MBIST Multiple ASIC Tape-out experience. Worked on full Chip design cycle from uArch development to Pre-Silicon and Post silicon validation. Protocol and Standards expertise : ARM SMMU, PCI Express, USB, MIPI M-PHY, xHCI, CHI/AXI/AHB/APB, NAND, SPI/QSPI, I2C/SMBUS HDL : Verilog and System Verilog ASIC CAD Tools expertise : DesignCompiler, PrimeTime, LEC conformal, DFT Compiler, VCS, NC, Spyglass, Verdi, MATLAB Other Interests : Algorithms, Computer Architecture, Data-structures and Machine learning. Goal : To master the art of design and have wide spectrum of domain expertise. Would strive to give something back to the industry which can be termed as game changer You can get in touch at vishalbhatt05@gmail.com

Experience

18 yrs 7 mos

Total Experience

2 yrs 3 mos

Average Tenure

7 yrs 8 mos

Current Experience

Nvidia

2 roles

Principal Engineer

Promoted

Jun 2023 – Present · 2 yrs 10 mos

Sr RTL design lead

Aug 2018 – Jun 2023 · 4 yrs 10 mos

Memory subsystem for next generation Tegra SoCs .

Intel corporation

RTL design lead

Jan 2018 – Aug 2018 · 7 mos · Bangalore

CPU core design group . core power management block RTL lead.

Juniper networks

ASIC Design Engineer 4

Mar 2016 – Dec 2017 · 1 yr 9 mos · Bangalore

Working on uArch and RTL coding for multiple blocks of next gen routing chips

Broadcom

Sr Staff - IC Design

Jul 2014 – Mar 2016 · 1 yr 8 mos · Bengaluru Area, India

Design engineer in the Infra & Networking group
Handling PCIe Gen1/2/3 , I2C/SPI/QSPI, DMAC and other IPs for processor subsystem
Some of the main responsibilities,
1. IP design and Spec expertise
2. Feature enhancement and developing new blocks (uArch + RTL coding)
3. Complete RTL ownership (Synth/CDC/Lint)

Synopsys

Sr. R & D Engineer

Jan 2012 – Jul 2014 · 2 yrs 6 mos · Bengaluru Area, India

Working as RTL design engineer with the USB-SSIC (Super-speed interconnect) IP design team. My responsibilities includes
RTL design
Synthesis
STA, Lint, CDC analysis
Supporting functional verification
Represented Synopsys in SSIC WG
Other major responsibility includes,
Handling customer cases.
Supporting other non SSIC features of the SNPS USB 3.0 cores like OTG 2.0/3.0
Mentoring junior engineers/interns/contractors.

Sibridge technologies pvt. ltd.

Member Technical Staff

Nov 2009 – Jan 2012 · 2 yrs 2 mos · Ahmedabad Area, India

USB3.0 Host Controller (xHCI 1.0) design
Contributed from specification understanding to micro-architecture design and RTL coding, functional verification, board brings up and tape out activities for USB3.0 IP development.
Worked on micro-architecture design and RTL coding for all the three layers from AHB interface to USB3 PIPE interface which includes xHCI, protocol and link layers.
RTL implementation for USB 3.0/2.0 Bulk (Including stream enabled transfers), Interrupt, Isochronous and Control transfers, Bandwidth management, Handling error and Flow control conditions, Link Power Management, scatter-Gather DMA for xHCI, Protocol and Link Layer.
Reused existing AHB interface IP and enhances it to support unaligned transfers and optimized for better throughput.
Actively involved in post tape-out activity like post-silicon validation, Understanding driver requirements and suggesting changes, working on throughput improvement, ECO etc
Actively participated in handling customer interaction and communication with design/verification teams working across multiple time zones.
Also worked on projects related to USB 2.0/OTG