Jul 2017 – May 2022 · 4 yrs 10 mos

• Design Validation
• ► Orchestrated a team of 4 professionals to develop test methodology for CMOS circuits, starting from test
• definition to pre-silicon simulations using System Verilog, post-silicon test implementation using
• Python, and design debug, resulting in early and robust test flow solution
• ►Performed electrical debug by micro-probing the silicon/FIB, measuring internal signals and capturing
• waveforms while providing stimulus to the DUT
• ►Collaborated with cross functional teams (Design, Sort, Test, Q&R, Systems) and key stakeholders (JDP
• Micron and IMFT) for test enablement to guarantee component margin to specification
• ►Recognized for significant business unit impact for root causing design issues whose key learning were
• fed forward to the next product cycle and helped improve testing methodologies
• ►Took responsibility in mentoring several new hires, ramping them up in key areas of the
• manufacturing flow
• ►Analyzed early customer returns with emphasis on driving test hole closure activities
• Mixed Signal Design
• ►Proficiency with logic/circuit design opened opportunity for a job rotation into a mixed signal design
• role, which helped build knowledge, expertise, and ownership for circuit blocks
• ► Interfaced digital and analog blocks as a feedback closed loop system for thermal sensor calibration,
• ran extensive HSPICE simulations to validate the worst-case PVT
• ► Designed HV and LV ring oscillators for monitoring process skew which helped with post-silicon debug
• including feedback to and from device development team
• ►Validated level shifters from functional checks, PVT, reliability and aging flow and timing performance
• Hi-Speed IO Yield Analysis
• ► Enabled our product to qualify Hi-Speed IO ATE Production by improving yield to more than 95% in
• the backend test flow
• ► Analyzed, monitored, and weekly reviewed volume data across a variety of multi-die packages,
• improving yield, binning capability, and reducing test time

Aug 2016 – May 2017 · 9 mos · Electrical Engineering Department, USC

• ◆ Research Link: http://alchem.usc.edu/portal/index.html
• ► Exploiting amorphous data parallelism in regular algorithms that uses dense arrays in the Galois system
• ► Running the same applications on a KDG(Kinetic Dependence Graphs) data structure which improves the speed and performance

May 2016 – May 2017 · 1 yr · University of Southern California

• ► Coordinate with the supervisors on managing the computing labs
• ► Supervise loaning the laptops, updating software and maintaining the labs

Oct 2014 – Jul 2015 · 9 mos · Gurugram, Haryana, India

• ► Worked as a CA LISA Developer to virtualize real time applications using CA LISA Tool
• ► Worked on Java platform.
• ► Was accountable for 6 developing projects and delivering them from offshore.
• ► Ensured compliance of policies for internal and client audits.
• ► Participated in team events and High Performance Delivery Platform(HPDP) for marketing our technology to clients.

Jun 2013 – Aug 2013 · 2 mos · India

• ► Researched about system designing and implementation of CCTV Cameras and Camera Sensors
• ► Visited Various Telecom Service Providers to understand the installation process of CCTV’s

Jul 2012 – Sep 2012 · 2 mos · India

• ► Built a working model of propeller clock and LED Cube using Atmel 8 bit AVR RISC microcontroller
• ► Extensively learned ethical hacking techniques

Jun 2012 – Aug 2012 · 2 mos · India

• ► Appointed as a Trainee with the aim of introducing a new web design (Canteen Management System ) for easy access of ordering and accounting of food consumables and for future reconciliation thereafter.
• ► Worked on PHP(Hypertext Preprocessor) technology.
• ► Training received under the Additional Director ,DRDO (Scientist 'F')
• ► Performed extensive software testing on the registration portal of DRDO.