Mar 2022 – Apr 2024 · 2 yrs 1 mo · Menlo Park, California, United States · On-site

Nov 2019 – Feb 2022 · 2 yrs 3 mos · San Francisco Bay Area

May 2017 – Nov 2019 · 2 yrs 6 mos · Hillsboro, Oregon

• Digital design (Frontend/RTL) of Fully Integrated Voltage Regulator (Analog Mixed Signal IP ). I have worked on implementation of power reduction features, power up sequence logic and the controller for the IP. I designed the logic to accept requests over different communication interfaces with the SOC & handle exceptions. I developed the RTL code around scan IP for implementing border and safety sealing and am responsible for CDC checks in the design.
• I am also involved in mixed-signal design and functional verification of the IP via behavioral model techniques that utilizes system-verilog with real number.

Sep 2016 – Apr 2017 · 7 mos · Hillsboro, Oregon

• Design Engineer in the Xeon Phi processor front-end DFX team. I developed RTL features around DFX IPs required for test and debug that includes TAP, Scan, Trigger block IP to initiate SoC actions, signal tracing architecture while providing test content support to pre-silicon validation team. I also worked on integration of IPs into the design.

Sep 2015 – Jul 2016 · 10 mos · Urbana-Champaign, Illinois Area

• As part of Masters Thesis, developed a mutual information based algorithm for selecting trace signals for post-silicon observation at communication interfaces of IPs. Used static information available during the planning and development phase such as protocol and interface specifications to automatically select the trace signals for the first tape out of chip. Used OpenSPARC T2 SoC for the analysis.

May 2015 – Aug 2015 · 3 mos · Hillsboro, Oregon

• Worked on protocol-guided trace signal selection for post-silicon debug using static information available during the planning and development phase. Implemented a tool which reads the protocol descriptions & other collateral and identifies a group of trace signals to observe at communication interfaces of IPs.

May 2013 – Jul 2013 · 2 mos · Lausanne Area, Switzerland

• An algorithm called Iterative Layering was proposed by the laboratory in the past. It is a pre-synthesis technique which uses SAT instances for checking whether functional dependency exists between a set of generated small circuits (bricks) and the input circuit. This is done by constructing a miter and giving it to a SAT solver. New bricks are generated and added until functional dependency exists.
• My work was to implement incremental SAT solving for functional dependency check in Iterative Layering. Whenever a new brick is added, incremental SAT solving uses the information learned while solving the previous instance for solving the current instance. This project was implemented in ABC software system, where Iterative Layering was already implemented as a command. Across various circuits, Incremental SAT solving led to 10%-90% decrease in time required to arrive at functional dependency of a circuit on a minimum set of bricks due to faster formulation and solving of the SAT problem

Jul 2010 – May 2014 · 3 yrs 10 mos · Mumbai Area, India

• During my undergraduate I was mainly interested in Digital Systems. Over the years I did courses and projects in Computer Architecture, Verification and Probability and Random Processes.
• As part of my final year Bachelor's Thesis I did a project on implementation of Machine Learning based algorithm in Gem5 simulator for incorporating DVFS in a Composite Core Architecture.