Sahil Sharma

Software Engineer

Noida, Uttar Pradesh, India16 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in PCIe and USB protocol development.
Led PCIe Gen4 IP development from scratch.
Strong background in RTL design and emulation.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in PCIe and USB protocols.

Contact

Skills

Core Skills

PcieUsbEmulationMemory DesignStatic Timing Analysis

Other Skills

ASICAlgorithmsCC++Circuit DesignClock Tree SynthesisData StructuresDebuggingDevice DriversEDAEmbedded SystemsField-Programmable Gate Arrays (FPGA)Logic SynthesisLow-power DesignNVMe

About

Currently: Microarhitecture and RTL coding for PCS layer for USB3.2/USB4/USB4v2 , PCIe , DP2.0, DP1.4, HDMI PHY IP/serdes. Having excellent knowledge of PCIe Gen 1/2/3/4/5 all layers: Transaction Layer, DataLink Layer, Physical Layer(logical), Configuration space, rx lane margining and Retimers. Expertise in PIPE specification till PIPE5.2/6.1. Actively involved in defining extra signal/interface/methodology required in PIPE, addressing shortcomings of PIPE5.2/PIPE6.1 Very good knowledge of USB 3.2 (3.x) and USB4/USB4v2 protocol. In Mentor Graphics: - Design Lead for PCIe Gen4-Gen5 IP design team and of PCIe transactor for emulation (Veloce) as per spec guidelines. Our team built whole PCIe IP core from scratch. Expertise and hands on experience for all layers and generations of PCIe(Gen 1-2-3-4-5). - Expertise in evaluating and optimizing performance in emulation for transactors. - Experience in developing USB 2.0 and USB 3.0 host transactors. - Basic knowledge of NVMe and OTN protocols. - Worked on developing accelerated and synthesizable Emulation Verification solutions for industry standard bus protocols like PCIe Gen4/5 and USB 2.0/3.0. - Module, SOC and system level design and verification (RTL/TLM) - Memory design(SRAM- L1/L2 cache), including static timing analysis(STA) and using low power concepts in STMicroelectronics(Senior Design engineer, 2010-2012) - Software Engineer at Samsung(2009-2010)

Experience

Synopsys inc

3 roles

Principal Engineer ASIC Digital Design

Feb 2024 – Present · 2 yrs 1 mo

Senior Staff engineer - ASIC Digital Design

Promoted

Feb 2023 – Feb 2024 · 1 yr

Staff Engineer, ASIC Digital Design

Mar 2019 – Feb 2023 · 3 yrs 11 mos

Into developing PCS layer of USB 3.2, USB4, PCIe (upto Gen4) for Synopsys DesignWare IP.
In depth knowledge of PCIe and USB protocols (PCIe up to Gen5, USB up to USB4)

USB 3.2USB4PCIeRTL designUSB

Mentor graphics

Member of Consulting Staff

Jun 2012 – Mar 2019 · 6 yrs 9 mos · Noida Area, India

As Design Lead:
Lead a team solely responsible for PCIe Gen4 IP development and PCIe Gen4 Transactor(Synthesizable accelerated VIP) development.
Architecture and Micro-architecture definition as per spec guidelines.
As an individual contributor:
Do new enhancements in PCIe IP core to make it more feature rich (RTL coding using system verilog)
Transactors development for PCIe, NVMe, xHCI-USB 2.0/3.0(with ULPI/PIPE interfaces).
responsibilities include but not limited to:
Developing the micro-architectural specification of complex design block(s)
Do RTL design and logic implementation of architecture as per industry standard spec
Responsible for the logic implementation of complex design block(s) using SV RTL/C++ coding techniques.
achieving high performance of transactors on emulation(Veloce).

PCIeRTL designSystemVerilogTransactor developmentEmulation

Stmicroelectronics

Senior Design Engineer in Static Memories

Apr 2010 – Jun 2012 · 2 yrs 2 mos

Design for Single port High Speed Memories taking proper care for various timing constraints(STA), power analysis, sense amplifier design, row decoders, customized latches design at CMOS level.

Static Timing AnalysisSRAM designPower analysisMemory design