Pawan Kumar Upadhyaya — CEO

18+ years of experience in IP Verification and Verification IP Development • GPU Verification (System Verilog – UVM) • DDR IP Verification (System Verilog – UVM) • PCIe Gen-5 IP Transaction Layer Module Level Verification (System Verilog – UVM) • PCIe Gen-4 IP Verification (DemoTB) (System Verilog – UVM) • Ethernet IP & Subsystem Level Verification (System Verilog – UVM) • Ethernet Verification IP Development (System Verilog – UVM) • LIN Verification IP Development (System Verilog – UVM) • JTAG Verification IP Development (System Verilog – UVM) • Ethernet Verification IP development in Ethernet R&D Team and ownership of following Ethernet interfaces. This also include a PSUI (PureSpec User Interface) which supports a System Verilog (SV) Layer on top of the e-core to cater SV Users including UVM & OVM. 1) MII (Media Independent Interface) 2) RMII (Reduced Media Independent Interface) 3) SMII (Serial Media Independent Interface) 4) GMII (Gigabit Media Independent Interface) 5) RGMII (Reduced Gigabit Media Independent Interface) 6) TBI (Ten Bit Interface) 7) RTBI (Reduced Ten Bit Interface) 8) SGMII (Serial Gigabit Media Independent Interface) 9) QSGMII (Quad Serial Gigabit Media Independent Interface) 10) 1000Base-KX 11) XGMII(Extended Gigabit Media Independent Interface) 12) XAUI (Extended Attachment Unit Interface) 13) RXAUI (Reduced Extended Attachment Unit Interface) 14) 10GBaser-KX4 15) XSBI (Extended Sixteen Bit Interface) 16) 10GBase-KR 17) 20GBase-R 18) 25/50G Interfaces 19) XLGMII (40 Gbps) 20) CGMII (100 Gbps) 21) 40GBase-KR4, 40GBase-CR4 22) 100GBase-KR10, 100GBase-CR10, 100GBase-KR4, 100Gbase-CR4 23) MDIO 24) ISO/OSI Model’s Upper Layer Frame Generation and Extraction Architecture for IPv4/IPv6, TCP/UDP, MPLS, SNAP, PTP, FC Layer Packets. • CPSW_3G(Common Platform Ethernet Switch - 3G) RTL Verification using Specman(e Language) • CPSW_3GF(Common Platform Ethernet Switch - 3GF) RTL Verification using Specman(e Language) • USB 3.0 eVC Development (Specman - e Language - eRM Compliant) • USB 2.0 eVC Development(Specman - e Language - eRM Compliant) • USB 2.0 RTL Verification using Specman(e Language) • Module Level Verification of PDP Logic Board using Specman(e Language) • AES RTL Design in Verilog HDL & its Verification using Specman(e Language)

Stackforce AI infers this person is a Semiconductor Verification Specialist with extensive experience in IP verification and development.

Location: Noida, Uttar Pradesh, India

Experience: 18 yrs 6 mos