Stanley Victor

Software Engineer

Bengaluru, Karnataka, India4 yrs experience

Key Highlights

  • Experienced in design verification methodologies.
  • Proficient in SystemVerilog and UVM.
  • Strong foundation in electronics engineering.
Stackforce AI infers this person is a Design Verification Engineer with expertise in semiconductor and electronics industries.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)Systemverilog

Other Skills

PerlVerilog

Experience

4 yrs
Total Experience
1 yr 4 mos
Average Tenure
--
Current Experience

Qicap.ai

Senior Design Verification Engineer

Aug 2021 – Feb 2024 · 2 yrs 6 mos · Bengaluru, Karnataka, India

PerlUniversal Verification Methodology (UVM)SystemVerilogVerilog

Acceletrade

Design Verification Intern

Aug 2020 – Jul 2021 · 11 mos · Bengaluru, Karnataka, India

Maven silicon

Design & Verification Trainee/Intern

Jul 2019 – Feb 2020 · 7 mos · Bengaluru, Karnataka, India

Education

Karunya Institute of Technology and Sciences

B.tech — Electronics Engineering

Jun 2015 – May 2019

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