Juned Rahi — Software Engineer
Strong Understanding in DFD (Design for Debug) for both Intel Architecture and ARM architecture SoC Design. Good knowledge of Computer Architecture, Digital Design and CPU/SoC Design Worked on UltraSoC and ARM Coresight debug strategies. Implemented various topologies and debug RTL using Python and JSON. Designing and implementing the various Debug topologies and IP integration. Developed Parameterized RTL and glue logic for better Post Si Debug. Hands on experience in Post Silicon Debug with cross site teams. Good knowledge in CDC, Lint, UPF, synthesis, timing constraints and timing closure. Provided manual ECO tcls for late RTL bug fixes or design change and ensured that it is FEV clean. Received Intel Awards: 2 DRAs (Department Recognition Award) and 2 HPG Quality Awards.
Stackforce AI infers this person is a highly skilled ASIC Design Engineer with expertise in SoC and Post Silicon Debug.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 2 mos
Skills
- Asic Design
- Debug Strategies
- Soc Design
- Post Silicon Debug
Career Highlights
- Strong expertise in DFD for SoC Design
- Hands-on experience in Post Silicon Debug
- Recipient of multiple Intel awards
Work Experience
ASIC RTL Design Engineer (3 yrs 4 mos)
Intel Corporation
SoC Design Engineer (4 yrs 6 mos)
SoC Design Intern (5 mos)
IEEE Robotics and Automation Society
Secretary (IEEE Student Branch) (11 mos)
Humanitarian Labs (HuT)
Research Assistant (1 yr 11 mos)
IEEE Signal Processing Society
Vice Secretary (IEEE Student Branch) (11 mos)
Education
Master of Technology - MTech at Birla Institute of Technology and Science, Pilani
Bachelor of Technology at Amrita University, Amritapuri Campus
Higher Secondary School at Navy Children School, Kochi
