Amandeep Singh

Co-Founder

Roorkee, Uttarakhand, India0 mo experience

Key Highlights

  • Led three successful silicon tapeouts.
  • Expert in VLSI design and In-Memory Computing.
  • Awarded Best Digital IC Tapeout twice.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and In-Memory Computing.

Contact

Skills

Other Skills

C (Programming Language)Field-Programmable Gate Arrays (FPGA)System on a Chip (SoC)

About

๐—ฃ๐—ต๐—— ๐—ฅ๐—ฒ๐˜€๐—ฒ๐—ฎ๐—ฟ๐—ฐ๐—ต ๐—™๐—ผ๐—ฐ๐˜‚๐˜€: I am a PhD researcher at IIT Roorkee, specializing in the design and hardware validation of high-performance In-Memory Computing (IMC) architectures for energy-efficient AI acceleration. ๐—ฃ๐—ต๐—— ๐—ฆ๐˜‚๐—ฝ๐—ฒ๐—ฟ๐˜ƒ๐—ถ๐˜€๐—ผ๐—ฟ: I am privileged to be working under the guidance of Prof. Bishnu Prasad Das. ๐Ÿ”— Faculty Profile: https://faculty.iitr.ac.in/~bpdasfec/ ๐—ง๐—ฒ๐—ฐ๐—ต๐—ป๐—ถ๐—ฐ๐—ฎ๐—น ๐—ฆ๐—ฝ๐—ฒ๐—ฐ๐—ถ๐—ฎ๐—น๐—ถ๐˜‡๐—ฎ๐˜๐—ถ๐—ผ๐—ป: My expertise includes developing time-domain computation techniques using specialized voltage-controlled and PVT-insensitive delay cells integrated with SRAM arrays to perform XAC and MAC operations, fundamental to BNN and CNN. ๐——๐—ฒ๐˜€๐—ถ๐—ด๐—ป ๐—š๐—ผ๐—ฎ๐—น๐˜€ & ๐—ฉ๐—ฒ๐—ฟ๐—ถ๐—ณ๐—ถ๐—ฐ๐—ฎ๐˜๐—ถ๐—ผ๐—ป: A core objective is to create IMC architectures that are linear, high-throughput, area-efficient, and energy-efficient. I verify performance using MNIST and CIFAR-10 datasets. ๐—™๐˜‚๐—น๐—น-๐—–๐—ต๐—ถ๐—ฝ ๐——๐—ฒ๐˜€๐—ถ๐—ด๐—ป ๐—˜๐˜…๐—ฝ๐—ฒ๐—ฟ๐˜๐—ถ๐˜€๐—ฒ: I possess end-to-end expertise across the entire VLSI design cycle, including architecture definition, custom circuit design, and full-chip physical implementation. ๐—ฆ๐—ถ๐—น๐—ถ๐—ฐ๐—ผ๐—ป-๐—ฃ๐—ฟ๐—ผ๐˜ƒ๐—ฒ๐—ป ๐—ฆ๐˜‚๐—ฐ๐—ฐ๐—ฒ๐˜€๐˜€: I have successfully led three silicon tapeouts in the TSMC 65 nm node for applications including neural networks (BNN and CNN) and the SHA-3 cryptographic algorithm. ๐—ง๐—ฒ๐—ฐ๐—ต๐—ป๐—ถ๐—ฐ๐—ฎ๐—น ๐—ฃ๐—ฟ๐—ผ๐—ณ๐—ถ๐—ฐ๐—ถ๐—ฒ๐—ป๐—ฐ๐˜†: I am proficient with industry-standard EDA tools, frameworks, and languages, including Cadence Virtuoso, Synopsys Design Compiler (DC), IC Compiler (ICC), PrimeTime (STA), HSPICE, Xilinx Vivado, FPGA prototyping, TensorFlow, Verilog, SystemVerilog, VHDL, TCL, Python, and C++. ๐—ฃ๐—ฟ๐—ฒ๐—บ๐—ถ๐—ฒ๐—ฟ ๐—”๐˜„๐—ฎ๐—ฟ๐—ฑ๐˜€: Recognized with the Best Digital IC Tapeout Award twice at the VLSID conference in 2025 and 2026. ๐—š๐—ฟ๐—ฎ๐—ป๐˜๐˜€ & ๐—™๐—ฒ๐—น๐—น๐—ผ๐˜„๐˜€๐—ต๐—ถ๐—ฝ๐˜€: Received grants from SERB and IEEE CAS for international travel, alongside multiple conference fellowships in India. ๐—ง๐—ฒ๐—ฎ๐—ฐ๐—ต๐—ถ๐—ป๐—ด & ๐— ๐—ฒ๐—ป๐˜๐—ผ๐—ฟ๐˜€๐—ต๐—ถ๐—ฝ: Contributed as a Teaching Assistant for Digital System Design on Coursera and transcribed courses for NPTEL. ๐—ฅ๐—ฒ๐˜€๐—ฒ๐—ฎ๐—ฟ๐—ฐ๐—ต ๐—ฃ๐˜‚๐—ฏ๐—น๐—ถ๐—ฐ๐—ฎ๐˜๐—ถ๐—ผ๐—ป๐˜€: I have authored three papers published in IEEE international conferences and journals, with an additional three papers currently in queue and under review. ๐Ÿ”— ๐—™๐—ผ๐—ฟ ๐—บ๐—ผ๐—ฟ๐—ฒ ๐—ฎ๐—ฏ๐—ผ๐˜‚๐˜ ๐˜๐—ฎ๐—ฝ๐—ฒ๐—ผ๐˜‚๐˜๐˜€ ๐—ฎ๐˜ ๐—œ๐—– ๐—ง๐—ฒ๐˜€๐˜๐—ถ๐—ป๐—ด ๐—Ÿ๐—ฎ๐—ฏ, ๐—œ๐—œ๐—ง ๐—ฅ๐—ผ๐—ผ๐—ฟ๐—ธ๐—ฒ๐—ฒ: https://lnkd.in/gJey4c25

Education

Indian Institute of Technology, Roorkee

Doctor of Philosophy - PhD

Aug 2020 โ€“ May 2026

Punjab Engineering College

Master of Technology - MTech โ€” VLSI Design

Jul 2018 โ€“ Jul 2020

Punjab Technical University

B.tech โ€” Electronics and Communications Engineering

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