Amandeep Singh โ Co-Founder
๐ฃ๐ต๐ ๐ฅ๐ฒ๐๐ฒ๐ฎ๐ฟ๐ฐ๐ต ๐๐ผ๐ฐ๐๐: I am a PhD researcher at IIT Roorkee, specializing in the design and hardware validation of high-performance In-Memory Computing (IMC) architectures for energy-efficient AI acceleration. ๐ฃ๐ต๐ ๐ฆ๐๐ฝ๐ฒ๐ฟ๐๐ถ๐๐ผ๐ฟ: I am privileged to be working under the guidance of Prof. Bishnu Prasad Das. ๐ Faculty Profile: https://faculty.iitr.ac.in/~bpdasfec/ ๐ง๐ฒ๐ฐ๐ต๐ป๐ถ๐ฐ๐ฎ๐น ๐ฆ๐ฝ๐ฒ๐ฐ๐ถ๐ฎ๐น๐ถ๐๐ฎ๐๐ถ๐ผ๐ป: My expertise includes developing time-domain computation techniques using specialized voltage-controlled and PVT-insensitive delay cells integrated with SRAM arrays to perform XAC and MAC operations, fundamental to BNN and CNN. ๐๐ฒ๐๐ถ๐ด๐ป ๐๐ผ๐ฎ๐น๐ & ๐ฉ๐ฒ๐ฟ๐ถ๐ณ๐ถ๐ฐ๐ฎ๐๐ถ๐ผ๐ป: A core objective is to create IMC architectures that are linear, high-throughput, area-efficient, and energy-efficient. I verify performance using MNIST and CIFAR-10 datasets. ๐๐๐น๐น-๐๐ต๐ถ๐ฝ ๐๐ฒ๐๐ถ๐ด๐ป ๐๐ ๐ฝ๐ฒ๐ฟ๐๐ถ๐๐ฒ: I possess end-to-end expertise across the entire VLSI design cycle, including architecture definition, custom circuit design, and full-chip physical implementation. ๐ฆ๐ถ๐น๐ถ๐ฐ๐ผ๐ป-๐ฃ๐ฟ๐ผ๐๐ฒ๐ป ๐ฆ๐๐ฐ๐ฐ๐ฒ๐๐: I have successfully led three silicon tapeouts in the TSMC 65 nm node for applications including neural networks (BNN and CNN) and the SHA-3 cryptographic algorithm. ๐ง๐ฒ๐ฐ๐ต๐ป๐ถ๐ฐ๐ฎ๐น ๐ฃ๐ฟ๐ผ๐ณ๐ถ๐ฐ๐ถ๐ฒ๐ป๐ฐ๐: I am proficient with industry-standard EDA tools, frameworks, and languages, including Cadence Virtuoso, Synopsys Design Compiler (DC), IC Compiler (ICC), PrimeTime (STA), HSPICE, Xilinx Vivado, FPGA prototyping, TensorFlow, Verilog, SystemVerilog, VHDL, TCL, Python, and C++. ๐ฃ๐ฟ๐ฒ๐บ๐ถ๐ฒ๐ฟ ๐๐๐ฎ๐ฟ๐ฑ๐: Recognized with the Best Digital IC Tapeout Award twice at the VLSID conference in 2025 and 2026. ๐๐ฟ๐ฎ๐ป๐๐ & ๐๐ฒ๐น๐น๐ผ๐๐๐ต๐ถ๐ฝ๐: Received grants from SERB and IEEE CAS for international travel, alongside multiple conference fellowships in India. ๐ง๐ฒ๐ฎ๐ฐ๐ต๐ถ๐ป๐ด & ๐ ๐ฒ๐ป๐๐ผ๐ฟ๐๐ต๐ถ๐ฝ: Contributed as a Teaching Assistant for Digital System Design on Coursera and transcribed courses for NPTEL. ๐ฅ๐ฒ๐๐ฒ๐ฎ๐ฟ๐ฐ๐ต ๐ฃ๐๐ฏ๐น๐ถ๐ฐ๐ฎ๐๐ถ๐ผ๐ป๐: I have authored three papers published in IEEE international conferences and journals, with an additional three papers currently in queue and under review. ๐ ๐๐ผ๐ฟ ๐บ๐ผ๐ฟ๐ฒ ๐ฎ๐ฏ๐ผ๐๐ ๐๐ฎ๐ฝ๐ฒ๐ผ๐๐๐ ๐ฎ๐ ๐๐ ๐ง๐ฒ๐๐๐ถ๐ป๐ด ๐๐ฎ๐ฏ, ๐๐๐ง ๐ฅ๐ผ๐ผ๐ฟ๐ธ๐ฒ๐ฒ: https://lnkd.in/gJey4c25
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and In-Memory Computing.
Location: Roorkee, Uttarakhand, India
Experience: 0 mo
Career Highlights
- Led three successful silicon tapeouts.
- Expert in VLSI design and In-Memory Computing.
- Awarded Best Digital IC Tapeout twice.
Education
Doctor of Philosophy - PhD at Indian Institute of Technology, Roorkee
Master of Technology - MTech at Punjab Engineering College
B.tech at Punjab Technical University