Ajesh M P — DevOps Engineer
keyskills:- VHDL verilog HDL DFT system verilog Modelsim Xilinx ISE FPGA
Stackforce AI infers this person is a VLSI and FPGA design expert with educational and managerial experience.
Location: Ernakulam, Kerala, India
Experience: 9 yrs 9 mos
Career Highlights
- Expert in VHDL and Verilog for FPGA design.
- Experienced educator and subject matter expert in VLSI.
- Managerial experience in automation and maintenance.
Work Experience
TESSMOTECH PRIVATE LIMITED
Automation Engineer (4 mos)
QA solvers
Education Professional (3 yrs 5 mos)
Unacademy
Educator and subject matter expert (5 yrs 2 mos)
ICCS College of Engineering and Management
Assistant Professor (9 yrs 7 mos)
Education
at M.E. VLSI DESIGN
