Vinod K.

Product Manager

Cupertino, California, United States15 yrs 6 mos experience
Highly Stable

Key Highlights

  • Innovative Verification Engineer with extensive SOC/IP experience.
  • Multiple publications in international conferences.
  • Deep understanding of standard interface IP and verification methodologies.
Stackforce AI infers this person is a highly skilled Verification Engineer in the semiconductor industry.

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Skills

Core Skills

Design VerificationModeling

Other Skills

5G Modem Design VerificationApplication-Specific Integrated Circuits (ASIC)DebuggingFunctional VerificationHardware ModelingMicroprocessorsModelSimMultisimOrcadPCI Express IP VerificationPCIePerforceSystem VerilogSystem on a Chip (SoC)SystemVerilog

About

To create technology that empowers people to change the world for the better. Engineer at heart and always an active learner. I am interested in technological innovation and enjoy problem-solving. I treasure great teams and together creating innovative products. My Philosophy: “We are what we repeatedly do. Excellence, then, is not an act, but a habit.” – Aristotle. "Nothing in the world can take the place of persistence" - Calvin Coolidge. * Innovative Verification Engineer with broad experience in SOC/IP Verification * Experience in hardware modeling for Interface IPs, MAC, and L2/L3 level protocols * Multiple publications in various international conferences (IEEE, PCIe-SIG, SNUG) * Deep understanding of the various standard interface IP(PCIe, PIPE, Ethernet, Automotive Ethernet), Verification methodologies (SV-based, UVM), hardware verification languages(System Verilog), and high-level programming language(C, C++) * Masters's Degree in Technology Management. * Intrinsic drive to deliver high-quality results that make a difference.

Experience

Nvidia

Design Verification

Nov 2024Present · 1 yr 4 mos · Santa Clara, California, United States

Apple

2 roles

Lead Design Verification Engineer

Promoted

Dec 2021Oct 2024 · 2 yrs 10 mos

  • Hardware Modeling
  • Design Verification
Hardware ModelingDesign Verification

Senior Design Verification Engineer

Dec 2019Nov 2021 · 1 yr 11 mos

  • Design Verification
Design Verification

Intel corporation

Design Verification Engineer

Mar 2018Nov 2019 · 1 yr 8 mos · Munich, Bavaria, Germany

  • 5G Modem Design Verification
5G Modem Design VerificationDesign Verification

Cadence design systems

Member of Consulting Staff

Jul 2016Mar 2018 · 1 yr 8 mos

  • Modeling and Verification of Leading Verification IP products - Ethernet/TSN/Converse IO
ModelingVerification

Mentor graphics

Lead Member Technical Staff

Apr 2013Jul 2016 · 3 yrs 3 mos

  • Modeling and Verification of Leading Verification IP products - PCIe
ModelingVerification

Hcl technologies

Member Technical Staff

Jul 2010Apr 2013 · 2 yrs 9 mos

  • Design Verification Engineer: PCI Express IP Verification.
Design VerificationPCI Express IP Verification

Education

Indian Institute of Technology, Delhi

Master of Business Administration - MBA — Technology Management

J.C. Bose University of Science and Technology, YMCA

Bachelor of Technology - BTech — Electronics and Instrumentation

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