Nikhil Thatikonda

Software Engineer

India10 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 8 years of experience in low power verification.
Expert in Universal Verification Methodology (UVM).
Strong background in DSP processor verification.

Stackforce AI infers this person is a Low Power Verification Engineer in the Semiconductor industry.

Contact

Skills

Core Skills

Universal Verification Methodology (uvm)Low Power VerificationRtl VerificationChip Design Verification

Other Skills

Unified Power Format (UPF)SystemVerilogClock gatingBOOTClocksIP VerificationInterfacesAssertionsDigital ElectronicsMicroelectronicsVerilogVLSIAnalog CircuitsMatlabRTL Design

About

As a Staff Engineer at Qualcomm with over 8 years of experience in low power verification of DSP and NSP processors, I contribute to advancing efficient processor design and functionality. My work focuses on leveraging clock gating, clocks, and Universal Verification Methodology (UVM) to ensure optimized performance and reliability. With substantial experience in DSP processor verification, I am committed to advancing low-power architecture verification. Collaborating with teams, I strive to develop innovative verification solutions that enhance processor efficiency and functionality while adhering to the highest industry standards.

Experience

10 yrs 10 mos

Total Experience

2 yrs 8 mos

Average Tenure

8 yrs 10 mos

Current Experience

Qualcomm

4 roles

Staff Engineer

Dec 2023 – Present · 2 yrs 5 mos

Low power verification of DSP and NSP processors

Universal Verification Methodology (UVM)Unified Power Format (UPF)SystemVerilogClock gatingLow Power Verification

Senior Lead Engineer

Promoted

Dec 2021 – Nov 2023 · 1 yr 11 mos

> Working in DSP processor verification team

RTL VerificationUniversal Verification Methodology (UVM)BOOTClocksIP VerificationUnified Power Format (UPF)+2

Senior Engineer

Dec 2018 – Nov 2021 · 2 yrs 11 mos

Engineer

Apr 2017 – Nov 2018 · 1 yr 7 mos

Arm

Engineer

Jul 2016 – Mar 2017 · 8 mos · Bengaluru, Karnataka, India

Consultant at ARM from VerifIQ technologies
>Worked in CPU verification team on Coverage analysis

Universal Verification Methodology (UVM)InterfacesAssertions

Broadcom

Engineer IC Design

Jul 2015 – Jun 2016 · 11 mos

Working on Chip Design Verification in WLAN team.
Written Perl scripts for finding the Leakage power of an IP at different corners like TT,SS,FF and different temperatures when Netlist and Standard cell libraries are given as input args.
Written Perl scripts for generalizing the data base such that there is no need to change the name of the files for every project.
Written perl scripts for parsing the data base files and extracting information and formatting it
Written perl script for converting a xls into a specified format for using it dynamically in another script
Working on Spyglass CDC Solution for Clock Domain crossings and lint checks at the top level of the chip using Atrenta Spyglass CDC solution .
Working on Quickturn (Palladium) Emulation .

Universal Verification Methodology (UVM)Chip Design Verification

Nvidia

INTERN

Jul 2014 – Dec 2014 · 5 mos · Bengaluru, Karnataka, India

Worked on the conversion of RTL to Gate level Netlist using Synopsis Design compiler tool
Worked on the Post Netlisting Activities like Netlist Auditor checks and also DC checks using inhouse tool to check the quality of the netlist produced ,to validate the design rules and also for sanity
Worked on the Meridian CDC tool to detect Clock domain crossing signals and eliminated the crossings upto 90% .
Worked on perl scripts for extracting information from the log files in the data base
CDC checks are also performed on the subsystem to detect metastability issues ,Data Loss and data coherency due to signals crossing domains and debug the issues using Multiflop synchronizer for a single bit signal and Mux Recirculation technique of FIFO for Bus signal.