Aug 2024 – Dec 2024 · 4 mos · Santa Clara, California, United States · On-site

• Interned in the CPU team focused on high performance Zen-series cores. Evaluated and benchmarked the complete PnR flow for Branch-Prediction Buffer tile using Fusion Compiler & PrimeTime to attain a target power value by introducing “clock-gating” cells and timing metrics by fixing high TNS/WNS timing paths.

Aug 2023 – May 2025 · 1 yr 9 mos · West Lafayette, Indiana, United States

• GTA for ECE 43700: Computer Design & Prototyping (Fall’23)
• GTA for ECE 33700: ASIC Design Laboratory (Spring’24)
• GTA for SoCET VLSI Team (Fall’23, Spring’24 & Spring‘25)

Jan 2022 – Jun 2022 · 5 mos

• In collaboration with DRDO, I worked alongside the AMS lab's PhD group to design and prototype an efficient, low-power SoC based on ARM Cortex-M0 for health-wearable applications. We performed the full SoC design flow to produce a GDSII with many area, memory and power optimization methodologies developed.
• This work has been accepted at the 2022 IEEE India Council Conference.

Jul 2020 – Dec 2021 · 1 yr 5 mos

• Working on the development of "5 Stage RV32-I processor on FPGA board for Edge Computing" under the guidance of Dr. Sujay Deb at the Advanced Multi-core Systems (AMS) lab in IIIT Delhi. The processor built on the board is capable of executing multiple RISC instruction sets, under full bypassing & stalling scenarios. An efficient, low-latency, low-power ECG signal processing application has been built on the RISC machine, which explores the domains like Near Memory Computation.

Jan 2022 – Jun 2023 · 1 yr 5 mos · Bangalore Urban, Karnataka, India

• Worked in the GCAD team with focus on Formal Verification activities, flows and methodologies in Qualcomm. Have signed-off multiple IPs ranging from Memory to Power Cores.

Jan 2021 – Jul 2021 · 6 mos · Delhi, India

• Working on an Independent project to propose & design a diagnostic circuit to raise alarms for impending write driver failures in SRAM memory under the able guidance of Dr Anuj Grover. A Write Driver design has been proposed, which employs the scheme of Negative Bitline level, but under the presence of ageing-induced resistive defects, writability of the cell degrades & hence is prone to failures. Therefore, a novel process & temperature-compensated test circuit has been designed to detect latent faults.
• The work has been accepted in IEEE APCCAS 2021, Malaysia

Aug 2019 – Dec 2021 · 2 yrs 4 mos · Delhi, India

• UTA for Digital VLSI Design, Integrated Electronics & Linear Algebra courses spanning over 2 years with responsibilities ranging from conducting weekly tutorials, labs to setting up exam papers and mentoring for course projects.

May 2020 – Jul 2020 · 2 mos · Bengaluru, Karnataka

• Deploy formal verification of one of the IP CORE designs based on DDR Cache Controller through tools like Synopsys VC Formal and Cadence Jasper Gold.
• Performed AHB Bus Certification for the registers in the RTL Design (FPV), performing Register checks to analyse the behaviour of the design (FRV) and debugging the failures using the Verdi tool.
• Analyzed FSM deadlock stage in the design using the formal linting process of the RTL design using JG Superlint.
• Using the AEP app, I performed Arithmetic Overflow Checks, Bound Checks, Conflicting Bus Checks on the RTL design and verified the design flaws.
• Made this flow a push-button solution by writing suitable Make files, Bind file, TCL scripts and generating IP-XACT file.
• Designed the Confluence Page (JIRA) fo the workflow of Formal Verification steps.
• Contributed in performing the Formal Signoff for a RTL design using the JasperGold FPV+COV tools.