Nilotpal Arjun

Director of Engineering

Delhi, India9 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Led a team of engineers in complex physical design projects.
Expert in timing closure and physical design methodologies.
Proficient in automation using TCL and PERL scripting.

Stackforce AI infers this person is a Semiconductor and Automotive Physical Design Engineer with strong automation skills.

Contact

Skills

Core Skills

Physical DesignTiming ClosureDrc ClosureCustom Clock Tree

Other Skills

Cadence InnovusTCLClock Tree SynthesisComplex CTSPERLVoltusVery-Large-Scale Integration (VLSI)Low-power DesignApplication-Specific Integrated Circuits (ASIC)Conformal LECSynthesisSRAMVerilogCDigital Electronics

About

To work as a successful engineer with my versatile approach in the interest of the project as well as with other challenging areas (project management, planning) and contribute in the growth of the company. I wish to involve myself in experience enhancing work, where my technical skills, engineering ability and practical exposure will be enriched.

Experience

9 yrs 2 mos

Total Experience

1 yr 11 mos

Average Tenure

2 yrs 3 mos

Current Experience

Hcltech

Senior Technical Lead

Feb 2024 – Present · 2 yrs 3 mos · India · Remote

Successfully led a team of 7 members during the implementation.
Netlist to GDS implementation of 7 blocks (1 Sub-System). It includes Floorplan, Power plan, place & route, clock tree synthesis, fixing DRC & LVS, and timing closure. Have seen high congestion issues in placement & did lot of experiments like padding, checker blockages, density screens etc, limiting routing tracks etc.
Did multiple experiments for convergence of timing in placement.
Had timing issues related to clock gating paths resolved with skewing experiments.
Done CTS experiments to meet latency requirements by creating skew groups.
Did Push & Pull experiments for critical paths in ECO stages.
Implemented timing ecos for the block, PV issues like DRC, LVS are analyzed & fixed.

Cadence InnovusPhysical DesignTCLTiming ClosureClock Tree Synthesis

Amd

Design Engineer

Sep 2022 – Feb 2024 · 1 yr 5 mos · India

Responsible for block closure on TSMC N3E.
Full timing and DRC closure of the block.
Complex CTS to reduce insertion delay which helped in better timing closure.
TCL automation for easy understanding of reports.

TCLTiming ClosureDRC ClosureComplex CTS

Stmicroelectronics

3 roles

Technical Lead

Promoted

Jun 2021 – Aug 2022 · 1 yr 2 mos

Worked with STMicroelectronics India in Automotive Product Group.
Have worked on complete netlist to GDS (physical design) as primary activity.
1. Responsible for full TOP/Block closure on 7nm TSMC FINFET.
2. Responsible for creating Custom Clock Tree for ID reduction for the macros present in the block.
3. Did PERL and TCL scripting and automation for easy understanding of reports.
4. PNR flow for dual voltage implementation.
5. Experienced in tools such as Innovus, Primetime, Formality, and Excellicon - Contree.

Cadence InnovusCustom Clock TreeTCLPhysical Design

Senior Design Engineer

Nov 2019 – Jun 2021 · 1 yr 7 mos

Subcontractor

Apr 2019 – Nov 2019 · 7 mos

Working with STMicroelectronics India in Automotive Product Group through HCL Technologies Noida.
Have worked on complete netlist to GDS (physical design) as primary activity.
1. Responsible for full Block closure on 7nm TSMC FINFET.
PNR -> Innovus and Signoff STA -> PT
2. Did PERL and TCL scripting and automation for easy understanding of reports and checklist creation at different PNR steps.
Also did additional TOP level STA analysis by changing the parameters like parasitics/derate/OCV factor/Noise window. Based on the various results certain analysis is done to help the Project.

Cadence InnovusTCLPhysical Design

Hcl technologies

Physical Design Engineer

Dec 2017 – Nov 2019 · 1 yr 11 mos · Noida Area, India

Worked on Dual Die Mixed Signal Radar Automotive SoC (2GHz, 16 & 28nm).
1. Did TOP level ( for 28nm die ) Floorplanning, PnR and PV fixes.
2. Improvising the existing EDA flow..
3. Custom Clock Tree for skew balancing and ID reduction.
4. Based on IR feedback some grid robustness is done to reduce the Static IR.
5. For reducing dynamic drop near clock cell, DCAP is placed adjacent to Clock Cell with scripting.
6. Custom Route for the analog IPs used.
7. Experienced in Cadence tools such as Innovus, Tempus and PVS.

Cadence InnovusPhysical DesignCustom Clock Tree