M

Mohith Varma

Software Engineer

Hyderabad, Telangana, India0 mo experience

Key Highlights

  • Strong foundation in digital design concepts
  • Hands-on experience with industry-standard tools
  • Passionate about cutting-edge semiconductor design
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI Physical Design.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

SynthesisClock Tree SynthesisFloorplanningPlacementRoutingPower OptimizationTcl ScriptingShell CommandsCadence GenusCadence InnovusCadence TempusDigital DesignsSignoffDigital ElectronicsApplication-Specific Integrated Circuits (ASIC)

About

I’m a passionate and detail-oriented VLSI Physical Design Engineer, currently building expertise through hands-on training and internship in RTL to GDSII flow. I have a strong foundation in digital design concepts and have worked with industry-standard tools like Cadence Genus, Innovus, and Tempus. With a Bachelor’s degree in Electrical and Electronics Engineering, I am highly motivated to contribute to cutting-edge semiconductor design and continuously improve my skills in timing analysis, floorplanning, placement, clock tree synthesis (CTS), routing, and signoff checks. I’m also buliding strong knowledge in areas like STA, IR drop, EM analysis, and power optimization techniques.

Experience

Sumedha institute of technology

ASIC Physical Design Engineer

Oct 2024May 2025 · 7 mos · Hyderabad, Telangana, India · On-site

  • Tools: Cadence - Genus, Innovus & Tempus
  • Hands-on experience in the complete RTL to GDSII flow using industry-standard tools like Cadence - Innovus & Genus.
  • familiar with process node such ad 28nm
  • Worked on floorplanning, placement, clock tree synthesis (CTS), routing, and static timing analysis (STA).
  • Performed DRC’s and ECO’s
  • Optimized designs to meet PPA (Power, Performance, Area) targets.
  • Gained deep exposure to timing closure, congestion analysis, and clock tree balancing.
  • Scripting and flow automation using Tcl and basic Shell commands.
  • Collaborated with a team of engineers and mentors to complete a block level project.
SynthesisClock Tree SynthesisFloorplanningPlacementRoutingStatic Timing Analysis+4

Education

Jawaharlal Nehru Technological University Kakinada (JNTUK)

Bachelor of Technology - BTech — Electrical and Electronics Engineering

Dec 2020May 2024

Narayana Junior College, Nellore

Intermediate — MPC

May 2018Mar 2020

Sri GVS high school, Gudur

10th — Mathematics

Jun 2017Apr 2018

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