Saurabh Patel — Director of Engineering

Experience in developing Hardware Verification Language (HVL) based constraint driven verification environment with methodologies like UVM (Universal Verification Methodology) and CDV (Constraint Driven Verification) for HDDC (Hard Disk Drive Controller), Processor IP, Network IP and Verification IP (VIP) etc. Experience on working with different stages of verifications like functional verification. Experience of achieving 100% code and functional coverage. Good hands on writing functional coverage. Experience of doing planning of projects and achieving that through continuous tracking. Worked on some of the complex protocols IP like UCIE , PCIE. Good skill of Test plan / Test case /Test bench development. Possess strong verification skills like random and advertising testing as well as debugging.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in advanced verification methodologies.

Location: Ahmedabad, Gujarat, India

Experience: 15 yrs