Nishant Tomar — Product Engineer
Verification Engineer with strong expertise in SoC and IP level verification using Verilog, SystemVerilog, and UVM methodology. Skilled in simulation, debugging, and coverage closure, with hands-on experience in RTL, GLS ( Gate Level Simulation), and Formal Verification. I have worked extensively on AMBA protocols (APB, AHB) and verified multiple SoC-level protocols/interfaces including I2C, SPI, UART, GPIO, IPCC, SCI, Ethernet, USB, SDMMC, Sysconf, TIMERS, and LPUART. Key strengths include: • Strong programming and debugging expertise in Verilog, SystemVerilog, C, and Shell scripting • RTL & GLS simulation and SoC-level verification • Testbench development, Testcase writing (SV/C-based), and failure debugging • Gate Level Simulation, Coverage closure, Functional & Formal Verification • Hands-on with industry-leading EDA tools (Cadence Xcelium/SimVision, VManager, JasperGold, QuestaSim, Verisium, IMC, Ncsim)
Stackforce AI infers this person is a Verification Engineer specializing in SoC and IP verification within the semiconductor industry.
Location: Noida, Uttar Pradesh, India
Experience: 5 yrs
Skills
- Soc-level Verification
- Gate Level Simulation
Career Highlights
- Expertise in SoC and IP level verification.
- Proficient in Verilog, SystemVerilog, and UVM methodology.
- Hands-on experience with industry-leading EDA tools.
Work Experience
HCLTech
Design Verification Engineer (3 yrs 3 mos)
Tata Consultancy Services
System Engineer (1 yr 9 mos)
Airports Authority of India
Trainee (2 mos)
Education
Post Graduate Diploma at Centre for Development of Advanced Computing (C-DAC)
B.Tech at Chandra Shekhar Azad University of Agriculture & Technology (CSAUA&T), Kanpur
Senior Secondary at Saraswati Vidhya Mandir
Secondary School at Saraswati Vidhya Mandir
