VIVEK KUMAR

Engineering Manager

Bengaluru, Karnataka, India12 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Led CAR verification for complex tapeouts.
Championed automation, reducing verification cycles.
Mentored a strong team of DV engineers.

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on SoC and low power domains.

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Skills

Core Skills

Soc VerificationClock And Reset Architecture VerificationVerification Methodology Development

Other Skills

CC++Cross-functional collaborationDebuggingDebugging and problem solvingDynamic simulation methodologiesFormal verificationHTMLInterpersonal and communication skillsManagementMicrosoft ExcelMicrosoft OfficeMicrosoft WordPhotoshopPower-aware verification

About

Experienced and results-driven Clocks & Reset Verification Manager at NVIDIA, with over a decade of expertise in functional verification of complex SoCs, specializing in clocking, reset, and low power domains. I lead high-performing verification teams to architect, implement, and deliver robust verification strategies for some of the most advanced chips in the industry. My work ensures first-silicon success for NVIDIA's next-generation products—ranging from AI accelerators to GPUs and automotive platforms—by validating mission-critical subsystems that are foundational to chip stability and performance. 🔧 Key Expertise: - Clock and Reset (CAR) architecture verification - SoC-level and IP-level CAR verification strategy and execution - Power-aware verification (UPF/CPF) and low power checks - Formal verification and dynamic simulation methodologies - RTL and DV infrastructure development for scalable verification - Cross-functional collaboration with architecture, design, DFT, and software teams 🚀 Highlights: - Successfully led the CAR verification for multiple complex tapeouts across NVIDIA’s AI, graphics, and automotive portfolios - Championed automation and reuse across projects, reducing verification cycles and increasing coverage - Mentored and scaled a strong team of DV engineers passionate about innovation and quality I take pride in enabling silicon that powers tomorrow’s technology—and thrive on solving tough challenges with elegance, efficiency, and impact. I am always eager to connect with other professionals in the industry to share insights and collaborate on cutting-edge projects. Let's connect and explore how we can drive the future of verification together.

Experience

Nvidia

2 roles

Hardware Engineering Manager

Promoted

Jun 2023 – Present · 2 yrs 9 mos

Clock and Reset architecture verificationSoC-level verificationPower-aware verificationFormal verificationDynamic simulation methodologiesRTL and DV infrastructure development+2

Senior Asic Engineer

Sep 2018 – Jun 2023 · 4 yrs 9 mos

Nxp semiconductors

Senior Design Engineer

Jan 2016 – Sep 2018 · 2 yrs 8 mos

Freescale semiconductor

Design Engineer

Jun 2013 – Jan 2016 · 2 yrs 7 mos · Noida Area, India

SoC Verification Engineer , having complete understanding of the flow of System level verification environment ,have worked on verification of COP (Common-On-Chip Processor) including complex IP's like Clocks , reset and Power Management.
My strong suites are:
✦ 5 years work experience in SoC verification team of Freescale/NXP Semiconductors.
✦ Worked on the crictal components of the SoC ( COP - Common On chip Processor ) including complex blocks like Reset, Clock Generation Unit, Clock control Unit, Power Management and Ethernet Controller.
✦ Worked closely with architects and RTL designers to develop a verification strategy and verify functional correctness of different modules in Soc.
✦ Good understanding of SoC architecture and verification flow.
✦ Strong knowledge and experience with RTL and gate-level/SDF simulation.
✦ Knowledge in protocols such as AXI and Freescale Internal Protocol (Sky-blue and Magenta) for on-chip. Communications and SoC control
✦ Strong debugging and problem solving skills
✦ Strong interpersonal, communication and management skills. I am always ready to grasp and learn something new.
Specialties: -
Verification improvements Methodology Development e.g. Pipeline Reset Value verification Flow, Soc Clock Monitor, Clock control Signals connectivity Verification Flow.
IC Design Environment, flows and tools throughout product life-cycle
UNIX, Microsoft office, MS Project, Primavera, FrameMaker,DesignPDM
Root Cause Analysis of debugs on validation and test failures
Functional coverage (Toggle + Code), Assertions and formal verifiers(PINS-verification)
Programming Languages: Verilog , System Verilog,C/C++
Simulation Tools : VCS
Waveform Debuggers: DVE(Synopsys), nWave(Cadence)
Formal Tools : VC Formal (Synopsys)