Gaurav Dave — Product Manager

Speciality: - ASIC Post Silicon Validation, ASIC SoC/IP Functional Verification using SystemVerilog (UVM, VMM) & Vera (RVM) - 15+ years of experience in doing post silicon validation, functional verification of ASIC SoCs & IPs and gate level simulations - Comprehensive experience in architecting and developing SoC and IP verification testbench components using HVLs like SystemVerilog, Vera & SystemC; and using verification methodologies like UVM, VMM, RVM & Client specific OOPs methodologies etc. - Involved in verification of SoCs like Networking domain(Ethernet - 400G/200G/100G/50G/FlexE1.0, OTN - 100 Gbps) and Audio/Video/UMTS at the system level as well at the block level. - Experience in debugging RTL simulation issues, interacting closely with RTL designers to resolve RTL issues and enhancing simulation performance. - Worked on creating test plans, functional coverage plans, code coverage / functional coverage analysis and gate level simulation debug while executing various projects. - Thorough experience in creating post silicon validation plan for ASICs, creating validation infrastructure and debugging ASIC board and tester issues during post silicon validation activities. - Technologies: Ethernet (50G/100G/200G/400G/FlexE1.0) OTN (100G), OFP OIF-SAR, OIF / Ethernet Interfaces (like SFI, OTL, SFI5, INTERLAKEN, SPI-3), AHB, DVB - Tools: VCS, Questasim, IUS, Simvision, ATDesigner - Scripting: Python, Shell Scripting using Bash, Makefiles

Stackforce AI infers this person is a seasoned ASIC verification engineer with expertise in post silicon validation and functional verification.

Location: San Jose, California, United States

Experience: 22 yrs 10 mos