Aug 2021 – Aug 2024 · 3 yrs · Bengaluru, Karnataka, India

• Working on Development of Novel Hardware Block to Improve the Performance between Cores & Memory Transaction in Server Class Processors. Developed a IP to enable Memory Pooling and Memory sharing between 2 Hosts and 4 Memories in a Server Stack via CXL.Mem. It including developing of a Hardware block which implemented Linked List Data Structure Algorithms. Silicon Proven and compliance with CXL 2.0 Specifications. Role and Responsibilities included:
• Architecture Core Team Member
• Micro-Architected and Owned Specifications for the IP
• Complete Ownership of the IP from Specifications to Implementation
• RTL Design
• Supporting Pre-Silicon and Post-Silicon activities
• CXL.Mem Transactional Layer Development
• Intel 7nm
• Mentoring Other Engineers to make them Independent Contributors and Team Players
• STA Specialist for Proposing and Implementing Logic to meet timing requirements for Low Latency - Met Design at 2GHz
• CDC Analysis and Implementation of CDC Blocks as per Custom Requirements
• Parallelization Architecture for given Logic to achieve Low Latency
• Server NOC Technical Readiness
• Core to Cache Memory Transaction Block Technical Readiness, Specifications and Optimizations
• Owned Process IP's to enable Guaging Process Efficiency

Feb 2018 – May 2019 · 1 yr 3 mos · Bengaluru, Karnataka, India

• Front-End RTL Fabrics (Network-On-Chip) Team Member
• To co-work with team on designing and implementing non-coherent
• fabrics (Network-On-Chip) for Converged Mobility, Entry Client and
• Modem Products.
• RTL Design and Integration.
• SOC Non-Coherent Fabrics Design Architecture Sign-off and Execution
• Planning.
• Ramping up new team members on Design Execution w.r.t Fabrics.
• Modifying/Proposing Enhancements in Fabrics IP’s.
• Support Functional Pre-Silicon and Post-Silicon Validation Debugs and test cases development.
• Reviewing CDC, UPF, Security, Registers Files and Debug signal lists of Intel Fabrics IP’s used in SOC.
• Give inputs to Power, Clocking, Fuse and DFT teams for supporting their requirements w.r.t message transactions through fabrics.
• Sync-Up with all IP teams having interface with Fabrics (NOC N/W) for signing-off on the requirements of interface.

May 2019 – Aug 2021 · 2 yrs 3 mos · Mumbai Metropolitan Region

• Design Architecture (For High Frequency Trading Algorithms)
• FPGA Based System Design
• RTL Design and Verification (Verilog and System Verilog)
• Specifications to Implementation
• NOC Architecture/Specification/Development For Intercommunication Between HFT Accelerators and Interface IP's
• Ethernet 10G MAC & PHY Layer Development
• PCIe TLP Unit Implementation
• Xilinx Hard IP's Optimised Usage For Low Latency - GTY Transceiver, QDMA, PCIe Integrated Block
• Complete Ownership Of Projects
• Working as a FPGA Lead
• Mentoring Other Engineers to make them Independent Contributors and Team Players
• STA Specialist for Proposing and Implementing Logic to meet timing requirements for Low Latency
• CDC Analysis and Implementation of CDC Blocks as per Custom Requirements
• Parallelisation Architecture for given Logic to achieve Low Latency

Oct 2017 – Feb 2018 · 4 mos · Bengaluru, Karnataka, India

• Working in RTL and Design Flow Team
• ASIC architecture, micro-architecture development, design and debug
• Coding readable, maintainable, verifiable and synthesizable logic in Verilog and/or System Verilog
• Logic synthesis, CDC, STA, formality, ECO process, tool flows and scripting
• Working on LPDDR4/DDR4 PHY and DFI
• Computer architecture/Processor fundamentals

Feb 2017 – Sep 2017 · 7 mos · Greater Hyderabad Area

• Worked In Consumer Mobile Solutions Team.
• Type C USB solutions
• MIPI I3C IP Development
• MIPI I3C Based Solutions
• Audio Processing IP (SPDIF to I2S Bridge)
• RTL Design And Verification
• Designing Architecture for a Design Implementation Using iCE40 family FPGA's of Lattice
• Hardware Characterization and Testing
• FPGA Based Designs Using Lattice FPGA families

Feb 2016 – Feb 2017 · 1 yr · Greater Hyderabad Area

• Working In Consumer Mobile Solutions Team.
• Type C USB solutions.
• MIPI Based Solutions
• RTL Design And Verification
• Hardware Characterization and Testing
• FPGA Based Designs Using Lattice FPGA families

May 2013 – Jul 2015 · 2 yrs 2 mos · Mumbai Metropolitan Region

• The work done here was from scratch. Have to not only build electronics firmware and hardware but also build proper environment in order to achieve the goals. Major part of work was in embedded C, simulators, micro-controller design's, board design's, pcb designing software's.
• Firmware Design and debugging
• RTL Design & Verification and FPGA Prototyping
• Electronics Circuit Design And Implementation using micro-controllers
• PCB Designing
• Electronics Product Design
• Electronics Inventory
• Leading Electronics Assembly Team

Apr 2012 – Apr 2013 · 1 yr · Mumbai Metropolitan Region

• Developed the avionics design in order to meet the problem statement of SAE AERO DESIGN Advance class competition rules. Worked in testing, procuring, making of things required for practical implementation.