Jun 2022 – May 2023 · 11 mos · Singapore · On-site

• Articulated the Firmware flow to verify wireless MCU based SoC . The Flow set is communion of several Python , C , GCC makeflow. Enabled the setup to be driven with VCS steps for MTK simulation flow.
• Involved in training team [size 10+] on MCU based or Processor based SoC verification. Managing the FW flow setup , integration and deployment for current project for subsystem teams and chip level DV teams across Taipei , Bangalore . Contributes regularly to flow activities for new and existing platforms using python/perl scripting.
• Technical skill upgrad : C/C++ usage, Python, Makeflow , Linker scripts attribute usage and ASM language.

Aug 2016 – May 2022 · 5 yrs 9 mos · India,Singapore

• Worked as Lead , to define and specify requirements for verification of feature BT-WLAN coexistence subsystem verification.
• Involved in resourcing, task allocation and scheduling along with technical responsibilities for various SOCs reusing this subsystem, focusing on IOT, wearables and WIN application specific SOCs.
• Domain expertise in Blutooth 5.0 , BLE 5.0 L2/L3 network IP Verification, IEEE 802.15.4 Zigbee and PTA communion communication protocol verification. Domain expertise handling design verification of bluetooth features TX diversity , RX antenaa deiversity , Dual link Layer , BT - WLAN - LTE RF coexistence .
• Design Verification Expertise: Constarined random driven verification techniques ,Assertion based protocol verification, developing verification components in System verilog and UVM methodology, involves developing Checker models, functional coverage models , Scoreboards. Expertise Gate level simulation and developing scripts to automate DV tasks.
• Tool Knowledge: VManager for DV regression management, deployed ICO Adaptive input generator Tool and case study with non-aigen SV simulation results , experience using PSS tool mentor graphics.
• Obtained IOS internal office shift opportunities to shanghaia and ireland too.

Jun 2010 – Mar 2016 · 5 yrs 9 mos

• Final Role as Lead for 3-member team and responsible for delivering design verification for IXTG101 FPGA based project wrapper on Infinera Client OAM supports 100G ethernet packets switching via serdes , PCIe lanes to OTN lines . Acquired Domain Knowledge on ITU-T-G709 OTN MAC blocks , OTN packet types and switching .
• Reused IP DV components and environment to sub-system bench. Used the concept of sequence layering to verify the FPGA wrapper for the IXTG101 with end-to-end scoreboard at OTN packet levels.
• Developing Validation Plan, writing CLI’s and delivering full end closure for validation of OAM SoC IXTG101, on FPGA, tested with MTIP core.
• Development of IP level testbenches in UVM, test planning for all the INFINERA Proprietary Network Interconnect IPs communicating with DWDM technology specific modules along fiber optic switches via, 9 packet processors between line and client-side traffic. The DV infrastructure in SV-UVM benches with monitors, drivers , scoreboards and functional coverage models for the IPs within XTN family.
• Learned and closed code coverage using code coverage metrics
• 2014 “U Rock” Award Winner: peer appreciation award given for relentless contribution across projects and good team spirit.
• Best Performer Q3,2014 For relentless effort as Module DV lead for XTFD block verification.
• Best Performer Q2, 2015: - IP level DV development and closure of the XTF framer verification and interoperability of the same with various OAM – SoCs.