Rutvik Patel

Software Engineer

Ahmedabad, Gujarat, India5 yrs 2 mos experience
Most Likely To Switch

Key Highlights

  • Expert in Universal Verification Methodology and SystemVerilog.
  • Strong background in ASIC and Digital Logic design.
  • Proficient in multiple programming languages including C and Perl.
Stackforce AI infers this person is a Digital Design Verification Engineer specializing in ASIC and VLSI technologies.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)SystemverilogAsicDigital LogicDigital Electronics

Other Skills

C (Programming Language)LinuxPerlVCSVLSIVerilog

Experience

Qualcomm

Senior Design Verification Engineer

Mar 2024 – Present · 2 yrs · Bengaluru, Karnataka, India

Universal Verification Methodology (UVM)SystemVerilogASICVerilogDigital LogicDigital Electronics

Synopsys inc

ASIC Digital Design Engineer II

Nov 2022 – Mar 2024 · 1 yr 4 mos · Bengaluru, Karnataka, India

ASICVerilogDigital LogicDigital Electronics

Einfochips (an arrow company)

Design Verification Engineer

Jan 2021 – Nov 2022 · 1 yr 10 mos · India

VerilogDigital LogicDigital Electronics

Education

Vishwakarma Government Engineering College

Bachelor of Engineering — Electronics and Communications Engineering

Jan 2016 – Jan 2020

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