Keyur Patel — Software Engineer
Experienced Validation Engineer with a demonstrated history of working in the information technology and services industry. Skilled in EDA, RTL Coding, Universal Verification Methodology (UVM), SystemVerilog, and Application-Specific Integrated Circuits (ASIC). Strong engineering professional with a Master of Engineering focused in Electronics and Communications(VLSI & Embedded System Design Engineering) from Gtu Pg School. I have known APB Protocols, FIFO, And sync RAM, and previously worked on those all projects. Previously working on DDR4, PCI4 gen, SOC and OTN, Now working on Ethernet 1G MAC , I have knowledge of FV(Formal Verification).
Stackforce AI infers this person is a Validation Engineer specializing in ASIC and SoC verification in the IT and services industry.
Location: Ahmedabad, Gujarat, India
Experience: 7 yrs 11 mos
Skills
- Functional Verification
- Universal Verification Methodology (uvm)
- Formal Verification
Career Highlights
- Expert in Functional Verification and UVM methodologies.
- Strong background in ASIC design and verification.
- Proficient in SystemVerilog and debugging complex systems.
Work Experience
VeriFast Technologies
Staff Engineer (5 mos)
Synopsys Inc
ASIC Digital Design, Staff Engineer (1 yr 1 mo)
Tech Mahindra Cerium Pvt Ltd
Senior Design Verification Engineer (1 yr 3 mos)
eInfochips (An Arrow Company)
Senior Design Verification Engineer (6 mos)
Verification Engineer (2 yrs 4 mos)
PerfectVIPs
Verification Engineer (1 yr 6 mos)
Indicus Technology
VLSI Design & Verification trainee (10 mos)
Education
Master of Engineering at Gtu Pg School
Bachelor of Engineering - BE at MERCHANT ENGG. COLLEGE, BASNA. VISNAGAR 065
