M N DADAPEER

Software Engineer

Andhra Pradesh, India6 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in IC&SOC verification across various cycles.
Hands-on experience in developing components from scratch.
Highly skilled in debugging complex test cases.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in verification methodologies.

Contact

Skills

Core Skills

Silicon DesignVerification

Other Skills

LpddrLpddr5DDR SDRAMUniversal Verification Methodology (UVM)VerilogAXIFormal VerificationAssertionsPCIeLogic DesignSystemVerilogDebugging

About

Adequate knowledge on IC&SOC verification in various cycles. Hands on experience in developing the components from scratch. Highly skilled in debugging the test cases. Command on Synopsys, cadence & Mentor graphic tools.

Experience

6 yrs 7 mos

Total Experience

3 yrs 3 mos

Average Tenure

3 yrs 6 mos

Current Experience

Amd

Sr. Silicon Design Engineer

Nov 2022 – Present · 3 yrs 6 mos · Hyderabad, Telangana, India

LpddrLpddr5Silicon DesignVerification

Sisoc semiconductor technologies pvt ltd.

3 roles

Sr. Verification Engineer

Promoted

Oct 2021 – Nov 2022 · 1 yr 1 mo

Design Verification Engineer

Oct 2019 – Oct 2021 · 2 yrs

ASIC Design verification trainee

Mar 2019 – Oct 2019 · 7 mos

Education

Sri Venkateswara University

Master of Technology - MTech — Communication systems

Jan 2016 – Jan 2018

JNTU Anantapur

Bachelor of Technology - BTech

Jan 2012 – Jan 2016

Stackforce found 100+ more professionals with Silicon Design & Verification

Explore similar profiles based on matching skills and experience

Neha Tabassum

ASIC Design and Verification Engineer

at Avalon Holographics

India8 yrs 5 mos exp

Sumit Goswami

Vice President of Engineering

at Qualcomm

Bengaluru, India25 yrs 5 mos exp

Customer engineeringDesign automationDesign implementationEDAHardware engineering

Saniya K.

Digital Verification Engineer - Lead

at NXP Semiconductors

Bengaluru, India7 yrs 7 mos exp

VerificationSoC VerificationIP VerificationVerification IP Development

Surendra Tadi

Principal Manager

at Qualcomm

Bengaluru, India22 yrs 8 mos exp

VerificationManagementDesign Engineering

Devesh Kumar

Principal Design Engineer

at Cadence Design Systems

Delhi, India14 yrs 10 mos exp

Functional VerificationOpen Verification MethodologySystemVerilogVHDLVMM

Suddarshan S

Technical Architect

at Tech Mahindra

Bengaluru, India19 yrs 10 mos exp

ASICVerification

VIVEK SARASWAT

Staff Engineer

at Qualcomm

Mathura, India10 yrs 4 mos exp

System on a Chip (SoC)Low power verificationDebugging

Payal Joshi

MTS Verification Engineer

at AMD

Bengaluru, India9 yrs 9 mos exp