Rishabh Mishra

VP of Engineering

Noida, Uttar Pradesh, India14 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC/SoC design and verification.
Led cross-functional teams for high-impact solutions.
Passionate about GenAI in verification workflows.

Stackforce AI infers this person is a leader in ASIC/SoC design and multimedia verification.

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Skills

Core Skills

AsicVerificationMultimedia VerificationTeam LeadershipVerification Ip Development

Other Skills

AMBA AHBAXIAlgorithmsApplication-Specific Integrated Circuits (ASIC)AssertionsCC++CompilersDebuggingDisplayPortEDAField-Programmable Gate Arrays (FPGA)Functional VerificationHDMII2C

About

Engineering leader with deep expertise in ASIC/SoC design and verification, specializing in GPU shader subsystems and multimedia pipelines. I’ve built SV/UVM testbenches from scratch and led cross-functional teams to deliver high-impact solutions. Passionate about applying GenAI and Agentic AI flows to transform verification workflows—boosting productivity and accelerating delivery. Skilled in AMBA, Multimedia (HDMI,DP, MIPI) protocols and committed to aligning technical excellence with strategic outcomes.

Experience

Qualcomm

Sr. Staff Engineer/Manager

May 2020 – Present · 5 yrs 10 mos

Leading shader subsystem DV team.
past : Gpu top Dv lead

Team ManagementDebuggingFunctional VerificationSystemVerilogUVMASIC+1

Synopsys india

R&D Manager/Lead Engineer

Aug 2012 – Apr 2020 · 7 yrs 8 mos · Noida, Uttar Pradesh, India

Leading multimedia transactor(aka AVIP) team for delivering the emulation friendly verification solutions for protocols such as MIPI CSI, MIPI DSI, MIPI SoundWire, HDMI, DisplayPort, I2C, UART, Video.
Architecture the solution for best performance.
Hands on RTL/C++ coding.
Driving functional verification
Team Management

Team ManagementDebuggingFunctional VerificationC++MIPIHDMI+4

Masamb electronics systems

Design Engineer

Aug 2011 – Jun 2012 · 10 mos · Noida, Uttar Pradesh, India

Responsible for developing the Verification IP using the System verilog and UVM. Worked on all aspects of Verification which includes BFM development, sequence creation, coverage model, assertions, testplan etc,

SystemVerilogUVMVerification IPAssertionsVerification IP Development