Indresh yadav — DevOps Engineer
I am Indresh Yadav, and I bring 12 years of experience in design verification, with a specialization in UVM-based verification methodologies. Over the years, I have worked on IP and subsystem verification across diverse domains, including avionics, security modules, and network-on-chip systems. I have hands-on experience in various areas, including project planning, translating requirements into verification test plans, bringing up UVM testbenches from scratch, implementing constrained random and metrics-driven verification, assertion-based verification, formal verification, emulation enablement, GLS verification, and functional/code coverage analysis and closure. My expertise spans protocols like AXI4, SPI, Ethernet, PCIe, and DDR4/LPDDR4, as well as scripting languages such as Python, Perl, and Shell. I have also had the privilege of mentoring junior engineers and helping them develop their skill sets. Currently, I am working as a Lead Design Verification Engineer at Boeing, where I lead a team of 12 engineers. I have contributed to key projects like the Boeing Autonomous System Computer (BASC) and Vehicle Management System Computer (VMSC). My responsibilities include project planning, developing UVM-based testbenches, integrating VIPs for protocols such as AXI4, PCIe, and Ethernet, and mentoring team members. I am passionate about verification and ensuring robust, high-quality designs through efficient verification strategies. I look forward to discussing how my experience can contribute to your team.
Stackforce AI infers this person is a Design Verification Engineer specializing in Aerospace and Hardware Verification.
Location: Ahmedabad, Gujarat, India
Experience: 13 yrs 3 mos
Skills
- Uvm
- Design Verification
Career Highlights
- 12 years of experience in design verification.
- Specialized in UVM-based verification methodologies.
- Led a team of 12 engineers at Boeing.
Work Experience
Boeing
Lead Design Verification Engineer (4 yrs 7 mos)
SVNTL Asia Pacific PTE
Sr Team Lead (1 yr 4 mos)
Ants Global (Pvt) Ltd.
Team Lead (3 yrs)
Cerium Systems
Sr Verification Engineer (6 mos)
eInfochips
Sr ASIC Engineer (2 yrs 9 mos)
ASIC Trainee Engineer (6 mos)
EITRA(Einfochip Training and Research Academy)
Trainee (7 mos)
IPR(Institute for Plasma Research)
Project Trainee (3 mos)
Education
Bachelor of Engineering (B.E.) at L.C. Institute of Technology
at RHHS