Diwakar Yadav — Software Engineer

Extensive experience in designing, developing, and executing comprehensive verification strategies for SOC/CPU designs. Proficient in SystemVerilog, UVM, and VHDL, with knowledge of industry-standard tools such as Verilog, ModelSim, and Synopsys Verdi. Strong understanding of verification methodologies, including testbench development and functional coverage models. Ability to debug complex issues, identify root causes, and implement efficient solutions. Hands-on experience with the AMBA protocol and its various components such as AXI, AHB, APB, etc. Ability to design and implement verification environments for AMBA-based systems, including both functional and performance-oriented tests. Familiarity with the RISC-V architecture and its specifications, including experience in verification of RISC-V based CPU designs. Demonstrated ability to troubleshoot and resolve issues related to RISC-V systems, and ensure the design meets or exceeds industry standards and customer requirements. Highly motivated and dedicated verification engineer with a strong attention to detail and problem-solving skills. Committed to ensuring SOC/IP/CPU designs meet or exceed industry standards and customer requirements.

Stackforce AI infers this person is a verification engineer specializing in ASIC and RISC-V technologies.

Location: Noida, Uttar Pradesh, India

Experience: 4 yrs 5 mos