Yesuraju Doppasani — Software Engineer
Experience in SOC and IP level Design and Verification.Good knowledge on system verilog and Verification methodologies(UVM/OVM).
Stackforce AI infers this person is a Design and Verification Engineer specializing in semiconductor and hardware verification.
Location: West Godavari, Andhra Pradesh, India
Experience: 9 yrs 4 mos
Skills
- Verification Methodologies
- System Verilog
Career Highlights
- Expertise in SOC and IP level Design and Verification.
- Proficient in System Verilog and UVM/OVM methodologies.
- Strong background in APU Verification at AMD.
Work Experience
AMD
Sr Silicon Design Engineer (3 yrs 8 mos)
Wafer Space - An ACL Digital Company
Design and Verification Engineer (4 yrs 1 mo)
FTech
Design and verification Engineer (1 yr 3 mos)
EMUG Engineering Services Pvt ltd
Graduate Engineering Trainee (4 mos)
Education
B.Tech at Ramachandra College of Engineering RCEE
Diploma at SIR C R REDDY POLYTECHNIC COLLEGE
school of secondary education at Z.P.O.H school
