Jun 2014 – May 2018 · 3 yrs 11 mos · London, United Kingdom

• Formal Verification Expert in Cadence UK and Scandinavia
• o Lead Pre-sales campaigns and work with Sales on strategy to win new clients
• o Fortify relationships with existing customers by working with RD and other AEs to ensure seamless Post-sales support
• o Formal Verification consulting/services to verify Cadence customer designs
• o Work closely with the Cadence AE team and customers to organize Cadence Club Formal conference in UK

Oct 2012 – Jun 2014 · 1 yr 8 mos · Watford, United Kingdom

• Solving Customer Verification Challenges using Jasper Formal
• o Successfully deployed Formal Verification techniques and JasperGold Apps like Structural Property Synthesis, X-Propagation Verification, Memory Register Bank Validation, Formal Coverage Metrics, Sequential Equivalence Checking, SOC Connectivity Verification, Post-Si Debugging and Security Path Verification
• o Worked closely with RD to implement enhancements and get issues fixed for customers
• o Designed and developed ATB & DFI 3 Proof Kits.
• o Protocol usage experience with AMBA 5 - CHI customer designs

Jul 2011 – Sep 2012 · 1 yr 2 mos

• ABVIP R&D Team Lead
• o Design and lead a team of engineers to develop Assertion Based Verification IP (ABVIP) for complex on-chip bus protocols using RTL & Assertions
• o Protocol design experience involves APB, AHB, AXI 3, AXI 4, ACE and OCP.
• o Support customers in verifying and converging on results for complex designs using advanced Formal Verification techniques

Mar 2008 – Jun 2011 · 3 yrs 3 mos

• Worked in the Incisive Formal Verifier (IFV) project as a Product Validation and Verification engineer
• Expertise areas in Formal Verification include User Defined Formal Analysis, Automatic Formal Analysis and Lint checking of designs
• o User Defined Formal Analysis includes assertion languages like PSL, OVL, SVA and IAL
• o Automatic Formal Analysis includes verifying a design using Deadcode checks, FSM checks, BUS checks, X-checks
• o Lint checking of designs to fix bugs at an early stage in the design cycle
• Worked on a project to model hard to detect stuck-at faults in the DFT domain using assertions and generate test patterns for the same.
• Quality responsibilities include Code coverage exercises to improve the quality of the code and improvement of error messages in IFV for better debug ability.
• Assertion Based Verification – Incisive Enterprise Manager (IEM) integration

Jun 2004 – Mar 2008 · 3 yrs 9 mos

• Worked in the Incisive Formal Verifier (IFV) project as a Product Validation and Verification engineer
• Expertise areas in Formal Verification include User Defined Formal Analysis, Automatic Formal Analysis and Lint checking of designs
• o User Defined Formal Analysis includes assertion languages like PSL, OVL, SVA and IAL
• o Automatic Formal Analysis includes verifying a design using Deadcode checks, FSM checks, BUS checks, X-checks
• o Lint checking of designs to fix bugs at an early stage in the design cycle
• Worked on a project to model hard to detect stuck-at faults in the DFT domain using assertions and generate test patterns for the same.
• Quality responsibilities include Code coverage exercises to improve the quality of the code and improvement of error messages in IFV for better debug ability.
• Assertion Based Verification – Incisive Enterprise Manager (IEM) integration

Jul 2009 – Sep 2014 · 5 yrs 2 mos · India

• Consulting Editor at Spiritz
• Writing has always been my passion. More so if the subject is poured in a glass and frosted to make an evening memorable. Wine Consultant, Food Critic, Bar & Lounge reviews are some of the hats I wear weaving words and recreating experiences every day.

Jun 2002 – Apr 2003 · 10 mos

• Junior Design Engineer – IP development
• Worked as a RTL-Designer coding in Verilog HDL.
• Developed RTL cores for a USB controller.
• Responsibilities included coding in Verilog and mentoring interns in projects involving Verilog and VHDL languages.