Dipesh Bajaj

Software Engineer

Bengaluru, Karnataka, India20 yrs 6 mos experience
Highly Stable

Key Highlights

  • Expert in ASIC and SoC design methodologies.
  • Proven leadership in semiconductor engineering roles.
  • Strong background in RTL design and verification.
Stackforce AI infers this person is a semiconductor engineering expert with extensive experience in ASIC and SoC design.

Contact

LinkedIn

Skills

Core Skills

AsicSoc

Other Skills

VerilogRTL designVLSIARMSystemVerilogStatic Timing AnalysisFPGADebuggingSemiconductorsEDAEmbedded SystemsICFunctional VerificationProcessorsPhysical Design

Experience

20 yrs 6 mos
Total Experience
4 yrs 5 mos
Average Tenure
2 yrs 8 mos
Current Experience

Arm

3 roles

Principal Engineer

Promoted

Sep 2023 – Present · 2 yrs 8 mos

ASICSoCVerilogRTL designVLSIARM+14

Staff Design Engineer

Promoted

Jan 2014 – Feb 2017 · 3 yrs 1 mo

Senior Design Engineer

Feb 2010 – Dec 2013 · 3 yrs 10 mos

Intel corporation

SoC Lead Design Engineer

Feb 2017 – Sep 2023 · 6 yrs 7 mos · Bangalore

Amd

2 roles

Senior Design Engineer

Promoted

Apr 2009 – Jan 2010 · 9 mos

Design Engineer II

Jul 2006 – Mar 2009 · 2 yrs 8 mos

Larsen & toubro

Graduate Engineering Trainee

Jul 2003 – Jun 2004 · 11 mos · Chennai, Tamil Nadu, India

Education

Indian Institute of Technology, Kanpur

Master of Technology (MTech) — VLSI and DISPLAY Technology

Jan 2004 – Jan 2006

SGSITS Indore

Bachelor of Technology (BTech) — Electronics and Instrumentation

Jan 1999 – Jan 2003

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