Karthik Baddam

Software Engineer

Amersham, England, United Kingdom21 yrs 1 mo experience
Highly Stable

Key Highlights

  • Expert in ASIC design flow from RTL to GDSII.
  • Proficient in digital verification methodologies like UVM.
  • Strong background in project planning and management.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and digital verification methodologies.

Contact

LinkedIn

Skills

Other Skills

VerilogPerlFunctional VerificationFPGASoCHardware ArchitectureRTL designVLSIModelSimComputer ArchitectureSimulationsOVM/UVM System VerilogFormal VerificationProject ManagementC

About

Experienced in ASIC design flow; from RTL through to GDSII. Core expertise in digital verification and advanced methodologies such as UVM and formal model checking. Hands on experience of working on projects with tight time scales, while keeping the customer needs in mind. Experienced in project planning and management of verification projects. Well versed in many programming languages inducing System Verilog, VHDL, Python, TCL and C++, also enjoys learning new programming languages. Specialities: System Verilog, VHDL, UVM, constrained random verification, formal, SVA, Python.

Experience

21 yrs 1 mo
Total Experience
4 yrs 2 mos
Average Tenure
4 yrs 2 mos
Current Experience

Qualcomm

Principal Formal Verification Engineer

Feb 2022 – Present · 4 yrs 2 mos · Cambridgeshire, England, United Kingdom

Arm

Staff Verification Engineer

Dec 2017 – Feb 2022 · 4 yrs 2 mos · Cambridge, United Kingdom

Huawei technologies

Senior Verification Engineer

Jan 2017 – Nov 2017 · 10 mos · Bristol, United Kingdom

  • Exciting and challenging verification work on an implementation of ARM CPU core

Imagination technologies

5 roles

Principal Verification Engineer

Promoted

Jul 2016 – Jan 2017 · 6 mos

Senior Hardware Design Engineer

Apr 2015 – Jul 2016 · 1 yr 3 mos

  • Part of the Advanced Verification Team in IMGWorks.
  • My work involved verification methodologies, guidelines, efficiency improvements, consultation and project work.

Leading Hardware Design Engineer

Apr 2014 – Mar 2015 · 11 mos

  • Part of the Advanced Verification Team in IMGWorks.
  • My work involved verification methodologies, guidelines, efficiency improvements, consultation and project work.

Leading Hardware Design Engineer

Promoted

Apr 2013 – Mar 2014 · 11 mos

  • Part of the PVR Graphics team.
  • My work involved verification methodologies and project work.

Hardware Design Engineer

Aug 2008 – Mar 2013 · 4 yrs 7 mos

  • My job involves hardware design, scripting, verification, methodologies and I am enjoying it.

University of southampton

PhD Student in ECS

Oct 2004 – Jul 2008 · 3 yrs 9 mos · Southampton, UK

  • Thesis Title: Differential Power Analysis Attack Resistant Designs at Logic Level
  • Work involved RTL to GDSII flows, FPGA prototyping, software development for
  • statistical analysis and netlist modification.

Education

University of Southampton

Doctor of Philosophy (Ph.D.) — Electrical and Electronics Engineering

Jan 2004 – Jan 2008

University of Southampton

MSc in Microelectronics System Design — Electrical and Electronics Engineering

Jan 2003 – Jan 2004

Jawaharlal Nehru Technological University

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 1997 – Jan 2001

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