Saket Kumar

Product Engineer

Delhi, India0 mo experience

Key Highlights

  • Expert in Static Timing Analysis and VLSI Design.
  • Strong foundation in Digital Circuit and Memory Design.
  • Proficient in Verilog and various timing tools.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Static Timing Analysis and Digital Circuit Design.

Contact

Skills

Core Skills

Static Timing AnalysisDigital Circuit Design

Other Skills

3D-EM (Wirebond & flipchip)C (Programming Language)Cadence VirtuosoDesign Rule Checking (DRC)EMXElectrical EngineeringElectromagnetic Simulation- Clarity3D SolverEngineeringEnglishHindiLatexLayout DesignLayout Versus Schematic (LVS)Mentor GraphicsMicrosoft Office

Experience

Cadence design systems

2 roles

Product Engineer II

Dec 2022Present · 3 yrs 3 mos

Static Timing AnalysisTempusSynopsys PrimetimeElectromagnetic Simulation- Clarity3D SolverEMX3D-EM (Wirebond & flipchip)+19

Product Validation Intern

Jul 2022Nov 2022 · 4 mos

Ntpc limited

Summer Trainee

Jul 2016Jul 2016 · 0 mo

Education

CDAC Noida

Master of Technology - MTech — VLSI

Jan 2020Jan 2022

Galgotias College of Engineering and Technology

Bachelor of Technology - BTech — Electrical and Electronics Engineering

BSEB PATNA

12th — Mathematics

St. Joseph Public School

10th

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