Swapnil Shashank

Software Engineer

Bengaluru, Karnataka, India18 yrs 7 mos experience

Highly Stable

Key Highlights

Expert in Low Power Verification for advanced semiconductor designs.
Proven track record in dynamic memory controller verification.
Strong foundation in SystemVerilog for SoC projects.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in low power and dynamic memory verification.

Contact

Skills

Core Skills

Low Power VerificationCortex-a15Dfi VerificationDynamic Memory ControllerVerificationSystemverilog

Other Skills

EARTTimerPMUAMBA Designer Plug-InIP-XACTAssertionsEnvironment StabilizationTestcase WritingFunctional VerificationAssertion Based VerificationSoCDevice DriversVerilogPerlASIC

Experience

18 yrs 7 mos

Total Experience

4 yrs 10 mos

Average Tenure

4 yrs

Current Experience

Intel corporation

2 roles

Graphics Hardware Engineer

May 2022 – Present · 4 yrs · Bengaluru, Karnataka, India

Component Design Engineer

Apr 2011 – Jul 2021 · 10 yrs 3 mos · Bengaluru Area, India

Vertex Shader and Domain Shader are 2 shaders, which have caches. Inherited environments were in AVMs, migrated them to UVMs and developed testbenches from scratch for Fulsim and Random environments. Developed scoreboards for SVR environments which are integrated with Fulsim environment as well. Developed geom_clt which consists of 6 units and achieved milestones for coverage well in advance.

Samsung electronics

Senior Staff

Jul 2021 – May 2022 · 10 mos · Bengaluru, Karnataka, India

Arm

Verification Engineer

Sep 2007 – Mar 2011 · 3 yrs 6 mos · Bengaluru Area, India

Sole responsible for Low Power Verification for Project Eagle (Cortex-A15) in ARM, Bangalore, which is ARM’s next generation Core. Apart from this, responsible for EART (Eagle Architecture Register table), Timer and PMU (Performance Monitoring Unit).
Worked on Project Nilgiri (PL-340) which is Dynamic Memory Controller with DFI (DDR PHY Layer). I was responsible for DFI verification and AMBA Designer Plug-In and IP-XACT for PL340 DMC.
Was working in SDD team but deployed in PDSV Team, which was responsible for Validation of Cortex-A8.

Transwitch

Intern

Jan 2007 – Jan 2007 · 0 mo · New Delhi Area, India

Worked in verification team, which was on Project verification of GPON SoC. It was a team of two verification engineers. We used SystemVerilog for the verification purpose and my role was to write Assertions, Environment Stabilization and writing testcases for the verification of the DDR SubSystem Block using VMM.