Abhilash Kaushal

Design Manager

Greater Toronto Area, Canada12 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 8 years of VLSI Design experience.
Expert in ATPG Pattern Generation and Silicon Debug.
Leadership in Scan Implementation for GPU SoC.

Stackforce AI infers this person is a VLSI Design Expert with a focus on ATPG and Silicon Debug.

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Skills

Core Skills

Atpg Pattern GenerationSilicon DebugDft Scan Architecture

Other Skills

ATPG - IDDQ, Burnin, Stuck-At, At-speed pattern GenerationATPG Pattern Generation and VerificationAtrenta SpyglassCC++Cadence ncsimCoverage AnalysisCoverage analysisDRC AnalysisMBIST VerificationMentor Tessent TestkompressPerlScan InsertionShell ScriptingSynopsys Tetramax

About

To build a Dynamic and challenging career working among smart,hardworking and passionate people which will enable me to utilize my technical and analytical skills to full extent. I am presently working as Sectional DFT Design Manager in RTG SoC Group with AMD, Canada & leading Scan/ATPG activities for a SoC chiplet and have more than 8 years of experience as a VLSI Design Professional. I have hands on experience on following core competencies - ATPG Pattern Generation and Verification (Stuck-at, At-speed, IDDQ, Burnin) - Translation/Merge of block level patterns to chip level patterns. - Verification of translated patterns through readback/simulation - Coverage Analysis - DRC Analysis - Design Integration - Silicon Bringup - Scan Insertion - MBIST Verification - Test Point Insertion - Silicon Debug Hands on Experience on- - Mentor Tessent Testkompress - Synopsys Tetramax - Cadence ncsim - Atrenta Spyglass with Knowledge of Perl, Shell Scripting, Verilog, C and C++

Experience

Amd

3 roles

DFT Manager

Jul 2023 – Present · 2 yrs 8 mos

DFT Sectional Manager

Nov 2020 – Jul 2023 · 2 yrs 8 mos

Leading the Scan Implementation for a discrete GPU SoC

Sr. Design Engineer

May 2018 – Nov 2020 · 2 yrs 6 mos

Translation/Merge of block level ATPG Patterns to Top level SoC patterns enabling efficient box packing minimizing white space and optimizing Scan channel Bandwidth utilization.
Pattern Validation of Translated patterns using Readback & Torte simulation
Intest/Extest ATPG, Top level Scan DRC, Coverage Analysis & Debug
Silicon Debug of complex SoC production patterns

ATPG Pattern Generation and VerificationTranslation/Merge of block level patternsVerification of translated patternsCoverage AnalysisDRC AnalysisSilicon Debug+1

Stmicroelectronics

2 roles

Technical Leader

Jul 2017 – May 2018 · 10 mos

Senior DFT Design Engineer

Nov 2015 – Jun 2017 · 1 yr 7 mos

ATPG - IDDQ,Burnin,Stuck-At,At-speed pattern Generation and simulation
Standalone IP verifications
DFT Scan Architecture- Clocking in Scan/LBIST/Standalone test modes
Developed understanding and hands on experience on Tetramax (Synopsys ATPG tool)

ATPG - IDDQ, Burnin, Stuck-At, At-speed pattern GenerationDFT Scan ArchitectureTetramax (Synopsys ATPG tool)ATPG Pattern Generation

Nxp acquires freescale semiconductor

DFT Design Engineer

Jun 2013 – Nov 2015 · 2 yrs 5 mos

ATPG Pattern generation, Coverage analysis, DRC Analysis and Pattern simulation.
Scan Insertion depending upon the scan strategy for performing partition level scan stitching.
EDT generation depending upon the scan compression strategy and flop count driven by various clock domains and integrating EDT into the design taking into account hard macro connectivity.
MBIST Verification-Pattern generation and simulation
Clocking verification at RTL level in different modes (Scan, At-speed, MBIST etc) through various controls in control unit.
Active involvement in Silicon Debug Activities.
Test point insertion in ATPG using Mentor testkompress tool to reduce the overall pattern count.

ATPG Pattern generationCoverage analysisDRC AnalysisScan InsertionMBIST VerificationATPG Pattern Generation+1