Rajesh Gottumukkala

Director of Engineering

Bengaluru, Karnataka, India19 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Proven track record in DFT and STA domains.
Successfully built and led multiple DFT teams.
Expertise in timing closure and silicon debug.

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with strong DFT and STA capabilities.

Contact

Skills

Core Skills

DftStatic Timing Analysis

Other Skills

RTL designSilicon DebugSTATiming closureLow Power DesignATPGSpyglassBISTFishtailDebuggingASICVLSISoCVerilogARM

About

Profound Knowledge in DFT and STA domains. Proven track record of execution on-time and first pass silicon. Excellent knowledge and hands-on experience in adjoining domains of RTL & PD. Specialties: ========= Physical Aware DFT Test Power/Test Time Reduction and Test Quality Improvement Static Timing Analysis and Timing Closure RTL Integration and Power Management STA Constraints Signoff Automation and Execution Efficiency Team Building

Experience

19 yrs 3 mos

Total Experience

4 yrs 9 mos

Average Tenure

7 yrs 3 mos

Current Experience

Google

3 roles

Senior Engineering Manager

Promoted

Oct 2020 – Present · 5 yrs 6 mos

Leading DFT Methodology & DFT CAD in Silicon team
Led SoC DFT in Next Generation Mobile SoC

DFTStatic Timing AnalysisRTL designSilicon Debug

Engineering Manager

Promoted

Apr 2019 – Sep 2020 · 1 yr 5 mos

Led DFT activities in Google's First Mobile SoC - Tensor
Built DFT team from scratch

DFTRTL design

Silicon Engineer

Nov 2018 – Mar 2019 · 4 mos

Samsung electronics

2 roles

Associate Director

Promoted

Mar 2018 – Nov 2018 · 8 mos

DFT Lead / Manager in Samsung FDS Group
Managed Multiple IP / SoC DFT in cutting-edge technologies
Built 20+ member DFT team to manage multiple SoC's in parallel

DFTRTL design

Senior Technical Manager

May 2017 – Feb 2018 · 9 mos

Mediatek

Project Lead

Jul 2014 – May 2017 · 2 yrs 10 mos · Bangalore

- Led Synth, STA & Timing closure teams for Modem & Mobile SoC

Texas instruments

4 roles

DFT Lead (SoC)

Dec 2012 – Jul 2014 · 1 yr 7 mos

Responsible for DFT Execution, Interaction with Cross domain (RTL/DV/STA/PD) and WW Product Engineering Teams for Infotainment (Automotive) SoC in 28nm Technology node.

STATiming closureStatic Timing Analysis

DFT Lead (IP)

Oct 2010 – Nov 2012 · 2 yrs 1 mo

Responsible for DFT Execution (which includes Low Power DFT Architecture Definition, Planning, Tracking and Delivering Quality Test patterns to multiple SoC teams) and Cross domain(RTL/DV/STA/PD) support/alignments for multi-standard, full HD video codec IP in 45nm(High Performance and Low Power) and 28nm Technology nodes

DFTSilicon Debug

Sr Design Engineer

Promoted

Jul 2008 – Sep 2010 · 2 yrs 2 mos

Responsible for DFT Implementation, Verification and Test patterns delivery for Cortex-R4 and DSP (C64X) IP’s in 65nm and 45nm Technology nodes. Worked on ATPG, Memory BIST, Boundary Scan and Silicon debugs extensively.

DFTLow Power Design

Design Engineer

Jul 2006 – Jun 2008 · 1 yr 11 mos

Involved in learning DFT and worked on DFT Logic Verification and Memory BIST / ATPG patterns generation for ARM9 & ARM11 designs in 65nm and 45nm Technology nodes.

DFTATPG