Yash Pratap Singh Sirohiya — Product Engineer

Working as Digital Design Engineer (FPGA) at Logic Fruit Technologies. -> Skilled in VHDL, Digital electronics, Static timing analysis -> Protocols : PCIe GEN5/6, I2C, SPI -> Aware of hardware testing and debugging -------------------------------------------------------- College Experience ¶ R&D Intern @Ministry of Electronics & IT, Government of India on E-mobility ¶ Selected as • Business analyst at Deloitte India (Full-Time) • Intern at NITI Aayog, GoI • Intern at Chennai Metro Rail Limited (CMRL) ¶ Publications : • National Conference : "Modeling, control & advantages of PMSM : EV's perspective" • International Conference (IEEE XPLORE) : "Review of electric vehicle motor technology : challenges & solutions" ¶ Technology enthusiast : EV motor technology, Connected vehicle, Urban mobility, IoT, Smart Grid (distributed generation), NLP (speech to text), Indian Science. Area of Interest : Control System, Digital Electronics, Motor Control, Motor design, Linear Algebra, Power Conversion Control, Signal & Systems ------ ------ ------- ¶ PORs : • Member, Training & Placement Cell, NIT BHOPAL • संयुक्त छात्र-अध्यक्ष, राजभाषा कार्यान्वयन समिति, एन० आई० टी० भोपाल (गृह मंत्रालय, भारत सरकार) • Unnat Bharat Abhiyan (by Ministry of Education) ¶ Interests : Public speaking, Debates, Hindi editor, article writing ¶ Hobbies : • Research on Scientific nature of Indian Knowledge System. • Study on technological developments for Indian languages. • Study on affordable and eco friendly technology for rural development. • Reviewing Government policies.

Stackforce AI infers this person is a Digital Design Engineer with a focus on E-mobility and FPGA technologies.

Location: Baran, Rajasthan, India

Experience: 6 yrs 2 mos