Anirudh S Bharadwaj

Product Engineer

College Station, Texas, United States2 yrs 4 mos experience

Key Highlights

Expert in RTL design and functional verification.
Hands-on experience with 5G technology and ASICs.
Proficient in FPGA design and simulation tools.

Stackforce AI infers this person is a specialized FPGA/VLSI design engineer with a focus on telecommunications and hardware solutions.

Contact

Skills

Core Skills

Functional VerificationAsicRtl Design5g Ran ArchitectureVerilogLogic Design

Other Skills

4G5G New Radio (NR)AcceleratorApplication-Specific Integrated Circuits (ASIC)DebuggingDigital ElectronicsField-Programmable Gate Arrays (FPGA)Functional TestingGate-level SimulationIntel Quartus PrimeModelSimO-RANPTP Network TimingPlace & RouteRouters

About

FPGA/VLSI design engineer with comprehensive experience in RTL design, functional simulation, synthesis, place & route, and timing analysis. Seeking to leverage my expertise in a challenging new role, contributing to advanced hardware solutions in the FPGA/VLSI design field

Experience

2 yrs 4 mos

Total Experience

9 mos

Average Tenure

Current Experience

Mirafra technologies

Verification Engineer II

Jun 2023 – Aug 2024 · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

As a consultant at Cisco, performed functional verification of ASIC network switch modules, focusing on the memory management unit
Involved in test case development, debugging, and improving code coverage.
Performed gate-level simulations to verify netlists, ensuring accuracy against RTL designs

Functional VerificationASICDebuggingGate-level Simulation

Mavenir

Graduate Engineer, Hardware

Sep 2022 – Jun 2023 · 9 mos · Bengaluru, Karnataka, India · On-site

Contributed to the RTL design and testing of key modules within Mavenir’s 5G Radio Unit, supporting multi-band and multi-carrier configurations using RFSoCs.
Developed expertise in 5G RAN architecture, Radio Unit architecture, functional testing, and PTP network timing for high-precision synchronization in 5G networks.

RTL Design5G RAN ArchitectureFunctional TestingPTP Network Timing

Saankhya labs pvt. ltd.

Intern

Jun 2022 – Sep 2022 · 3 mos · Bengaluru, Karnataka, India · On-site

Ramped up on RTL design techniques for FPGA implementation. Developed key building blocks such as a simple processor with a limited instruction set and an FIR filter using fixed-point format, implemented in Verilog HDL.
Verified functionality with ModelSim to ensure design accuracy and performance.

RTL DesignVerilog HDLModelSimVerilog

Intel corporation

Intern

Sep 2021 – Oct 2021 · 1 mo · Bengaluru, Karnataka, India

Developed logic modules like a Round Robin Arbiter, Traffic Light Controller, Calculator, and other foundational components using Intel DE1-SoC FPGA (Cyclone V and Max10)
Developed expertise in Intel FPGA design flow, including RTL Design, Simulation, Synthesis, Place & Route, and Timing Analysis.

Logic DesignRTL DesignSimulationSynthesisPlace & RouteTiming Analysis