Ankur Goel

CTO

Noida, Uttar Pradesh, India20 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in SRAM and DRAM architectures.
Proven track record in team management and mentoring.
Significant contributions to cutting-edge semiconductor technologies.

Stackforce AI infers this person is a Semiconductor Engineering expert with strong leadership in memory architecture design.

Contact

Skills

Core Skills

SemiconductorsCircuit DesignSramDramCompiler Design

Other Skills

3D-COC DDR3ASICAnalogApplication-Specific Integrated Circuits (ASIC)ArchitectureCCMOSElectronicsFDSOIFINFETFloorplanningGPIOIP PlatformsInnovationsIntegrated Circuit Design

About

Semiconductor Professional with experience of developing multiple IP Platforms in planar/FINFET, FDSOI technologies. SRAMs based Single Port/multi port memories, Std Cell design, GPIO, Tests chip. Experience in building and managing teams, training and mentoring of engineers, Excite Engg. teams to achieve high standards and retaining talent through motivation, engagement and coaching. Skilled in SRAM and DRAM Architectures and expertise in CMOS Complex Circuits design like RD/WR Assist circuits, level shifters, power gating, etc. and Silicon Debugging. Strong professional with a Master of Technology (M.Tech.) focused in MicroElectronics and VLSI Design from IIT Kanpur.

Experience

Arm

2 roles

Technical Director

Promoted

Apr 2019 – Present · 6 yrs 11 mos · Noida Area, India

Design of IP Platforms in planar/FINFET, FDSOI technologies: SRAMs based Single Port/multi port memories, Std Cell design, GPIO, Tests chip. Working with various IP teams on platform development consisting of multiple IPs, working closely with customer and foundry, managing people.

SemiconductorsSRAMCircuit DesignIP PlatformsFINFETFDSOI+1

Senior Manager, Engineering

Jul 2013 – Mar 2019 · 5 yrs 8 mos · Noida Area, India

Design of High Density, Low Power and High Performance SRAMs in nanometer CMOS planar/FINFET technology. Solid experience in developing memory architectures and circuit design/characterization of SRAM and DRAM memories, both embedded memories as well as full chip memories. Expertise in design of complex memory circuits like read/write assist circuits, sense-amplifiers, level-shifters, power gating circuits etc. Good experience in leading big teams for developing scratch and porting based memory platforms as per the business need. Pre-sales activities for memory platforms.
People Management : Building and managing teams, training and mentoring of engineers, Excite Engg. teams to achieve high standards and retaining talent through motivation, engagement and coaching.

SRAMDRAMCMOSMemory ArchitecturesCircuit DesignPre-sales

Lsi r &d pvt. ltd. bangalore

Circuit Design Lead

Apr 2010 – Jul 2013 · 3 yrs 3 mos · Bangalore

Developed Multi feature SRAM compilers at advanced technologies. Proposed and Incorporated several new circuits and techniques into SRAM Memories which made the products competitive and worked well into silicon. These schemes are expected to be used in next generation SRAMs as well. Proposed New SRAM Architectures which got converted to SRAM Compiler. Led Advanced Architecture team from India design Centre. Worked on PreSales for customer quotes.

SRAMCircuit DesignArchitecturePre-sales

Edison semiconductor

Senior Design Engineer II

Apr 2006 – Mar 2009 · 2 yrs 11 mos · Bangalore

After 6 months of technical training at Elpida Memory JAPAN, we started designing DRAM from scratch at Edison Semiconductor Bangalore. In just 3 years time span, the team did 2 projects. One out of these was world's smallest size DRAM. In this assignment I got an opportunity to work in almost all kind of circuits that are used in DRAM (charge pumps, voltage regulators, Bandgap references, DLL, sense-amp, level shifters etc.). We introduced several innovations in the product which helped the team to come-up with world's smallest DDR1 for the given frequency (as per the information from marketing). The DDR1 was a great success in first time silicon.
Developed few architectures for 3D-COC DDR3. Proposed a new TSV testing scheme.
Worked on PCM (phase change memory) for a small duration and developed an offset compensation scheme for phase change memory applications.

DRAMCircuit DesignInnovations3D-COC DDR3

St-microelectronics

Design Engineer

Jul 2004 – Apr 2006 · 1 yr 9 mos · Noida Area, India

Worked on SRAM compiler design at 65nm CMOS technology which was latest at that time. Worked on 3 SRAM compilers, 2 of which were development from scratch. All these compilers worked well in silicon. I got an opportunity to learn and design almost all common SRAM circuits and various architectures and trade-offs.

SRAMCMOSCompiler Design