Jul 2017 – Mar 2022 · 4 yrs 8 mos

• Site Manager for Silicon Package Board Business Unit in Noida. Responsible for development of site to contribute to company in innovation and product ownership. Site has developed multiple new products from scratch and delivered to customers - for individual users, mid size and enterprise level organizations. Collaborate with distributed teams to define product roadmap and ensure realization of product vision through execution. Experience in working with multiple accounts in different geographies. Manage, hiring and mentoring of engineering team. Responsible for technical guidance, resource and project management for the Silicon Package Board business unit in Noida.
• Process - Work with teams to identify improvements to product delivery, software development best practices, agile practices, software automation, customer beta engagements.
• Product Delivery – Allegro Front End and Allegro Pulse
• o Working with technical and product marketing for defining roadmaps and products positioning of existing products and identify new products.
• o Working with distributed engineering teams for product development
• o Directly engaged with multiple customers in USA and Europe
• o Work with sales teams for product renewals and customer displacements
• o Define best practices for software quality
• o Member of Cadence Patent committee – Responsible for reviewing inventions for patentability
• Member of Cadence Worldwide Patent Committee - In this role responsible for reviewing inventions for patentability

Jan 2007 – Jul 2017 · 10 yrs 6 mos

• Noida Site leader for Silicon Package Group at Cadence. Work closely with HR and Admin teams to ensure a good work environment, create a collaborative culture across different teams and functions, engage with teams on innovation and process improvement.
• Working with technical and product marketing for defining roadmaps and products positioning of existing products and identify new products. Responsible for the delivery of SPB next generation platform for products. Platform definition and delivery for next generation products. Delivered next generation logical authoring solution based on the platform.
• Responsible for providing architectural direction for a set of logic design capture set of products. The external component of this role requires presenting the architecture to other business units and customers. Worked directly with major customers like Intel, Nortel, Freescale, CISCO.
• Researching new paradigms for capturing hardware design architecture at a higher level of abstraction and building linkages to design implementation tools.

Oct 2004 – Oct 2007 · 3 yrs

• Table and HDL based design environment
•  Conceived a new patented paradigm for design entry based on spreadsheets.
•  Designed a schema for supporting concurrent changes in tools and proposed a smart differencing engine for updates. Patent pending.
•  Responsible for specifications, architecture and execution of an integrated environment supporting multiple design entry paradigms (spreadsheet, Verilog, VHDL), team design, high speed constraints solution and integration with simulators.
• Integration RF blocks inside Concept HDL PCB design
•  Architected and implemented the flow for integrating RF blocks inside Concept HDL PCB solution
•  Drove the Beta of the solution with Nortel Networks
•  Worked with Motorola, Phoenix for implementing their flow
• Chair of Cadence India Technical Conference, 2006. Responsible for organizing the technical and logistics of the conference.
• Member of Silicon Package Board patent committee. The charter of this team is to review and approve invention disclosures for patent filing

Jan 1994 – Jan 1994 · 0 mo