Paras Gupta

Software Engineer

Bengaluru, Karnataka, India14 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 10 years of experience in VLSI industry.
Expertise in MIPI specifications for camera and physical layers.
Proficient in RTL design and verification methodologies.

Stackforce AI infers this person is a VLSI design expert with extensive experience in semiconductor industry.

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Skills

Core Skills

VlsiAsic DesignFunctional Verification

Other Skills

ASICAlgorithmsC++Computer ArchitectureData StructuresDebuggingDigital ElectronicsEmbedded SystemsEmulationIntegrated Circuit DesignMIPI specificationsPost-Silicon bring-upRTL designSoCSystem Verilog

About

B.Tech in Electronics and Communication from "Indian Institute of Information Technology-Allahabad", holding 10+ years experience in VLSI industry with focus on verification and design of complex IP's. Have interest and experience in: -> Solving the various challenges which come in designing of new IP's, by leveraging learning in design and verification methodologies. -> Creating uarch and work on the design of IPs. -> Have past experience in unit level verification and design. -> Familiar with pre silicon emulation/fpga. -> Experience of handling post silicon bringup. -> Expertise in various MIPI Specifications for camera like CSI-2 -> Also have expertise in MIPI Specifications for Physical layers like D-Phy 1.1, D-Phy 1.2 and C-Phy Languages :Verilog, System verilog, C,C++. Scripting language like perl/python.

Experience

Nvidia

3 roles

Senior ASIC Design Engineer

Promoted

Apr 2014 – Present · 11 yrs 11 mos

Worked on the Design of Memory subsystem IP in Nvidia GPU pipeline. Have worked on multiple IP and multiple projects with focus on creating microarchitecture and coding RTL in verilog along with running synthesis, timing checks, and maintain high quality design.
In past worked on development of next generation camera IP for Tegra chip.
Had the opportunity to work on verification of the IP using UVM methodology.
Also, got exposure on related MIPI specs, and developed understanding of the various protocols used in camera subsystem.

VerilogRTL designUVM methodologyMIPI specificationsVLSIASIC Design

ASIC engineer

Jul 2012 – Mar 2014 · 1 yr 8 mos

Worked in an IP team and had the opportunity to get familiarized and work on different aspects of chip design flow including Front-End verification, Emulation and Post-Silicon bring-up for the designated units.
During this period gained experience with different tools and languages like VCS, verilog, system verilog, Perl.

VerilogSystem VerilogPost-Silicon bring-upEmulationVLSIASIC Design